Home
last modified time | relevance | path

Searched refs:iobase (Results 1 – 25 of 97) sorted by relevance

1234

/external/u-boot/drivers/net/
Dravb.c123 void __iomem *iobase; member
154 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0)) in ravb_send()
155 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0); in ravb_send()
221 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC); in ravb_reset()
224 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR, in ravb_reset()
242 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT); in ravb_base_desc_init()
346 eth->iobase + RAVB_REG_MAHR); in ravb_write_hwaddr()
348 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR); in ravb_write_hwaddr()
357 writel(0, eth->iobase + RAVB_REG_ECSIPR); in ravb_mac_init()
360 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR); in ravb_mac_init()
[all …]
Dsni_ave.c135 phys_addr_t iobase; member
182 return readl(priv->iobase + addr); in ave_desc_read()
206 writel(val, priv->iobase + addr); in ave_desc_write()
245 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); in ave_mdiobus_read()
248 mdioctl = readl(priv->iobase + AVE_MDIOCTR); in ave_mdiobus_read()
249 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); in ave_mdiobus_read()
251 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, in ave_mdiobus_read()
260 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); in ave_mdiobus_read()
271 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); in ave_mdiobus_write()
274 writel(val, priv->iobase + AVE_MDIOWDR); in ave_mdiobus_write()
[all …]
Dsmc91111.h71 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
72 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
74 unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
80 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
81 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
83 unsigned int __p = (unsigned int)((a)->iobase + (p)); \
91 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
92 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
94 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
95 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
[all …]
Duli526x.c209 u32 iobase; in uli526x_initialize() local
218 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); in uli526x_initialize()
219 iobase &= ~0xf; in uli526x_initialize()
233 dev->iobase = iobase; in uli526x_initialize()
241 db->ioaddr = dev->iobase; in uli526x_initialize()
246 printf("uli526x: uli526x @0x%x\n", iobase); in uli526x_initialize()
350 update_cr6(db->cr6_data, dev->iobase); in uli526x_disable()
351 outl(0, dev->iobase + DCR7); /* Disable Interrupt */ in uli526x_disable()
352 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5); in uli526x_disable()
458 outl(0, dev->iobase + DCR7); in uli526x_start_xmit()
[all …]
Dpcnet.c97 outw(index, dev->iobase + PCNET_RAP); in pcnet_read_csr()
98 return inw(dev->iobase + PCNET_RDP); in pcnet_read_csr()
103 outw(index, dev->iobase + PCNET_RAP); in pcnet_write_csr()
104 outw(val, dev->iobase + PCNET_RDP); in pcnet_write_csr()
109 outw(index, dev->iobase + PCNET_RAP); in pcnet_read_bcr()
110 return inw(dev->iobase + PCNET_BDP); in pcnet_read_bcr()
115 outw(index, dev->iobase + PCNET_RAP); in pcnet_write_bcr()
116 outw(val, dev->iobase + PCNET_BDP); in pcnet_write_bcr()
121 inw(dev->iobase + PCNET_RESET); in pcnet_reset()
126 outw(88, dev->iobase + PCNET_RAP); in pcnet_check()
[all …]
Dftmac100.c27 phys_addr_t iobase; member
35 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in ftmac100_reset()
56 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in ftmac100_set_mac()
71 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in _ftmac100_halt()
81 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in _ftmac100_init()
186 struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; in _ftmac100_send()
297 dev->iobase = CONFIG_FTMAC100_BASE; in ftmac100_initialize()
303 priv->iobase = dev->iobase; in ftmac100_initialize()
398 pdata->iobase = devfdt_get_addr(dev); in ftmac100_ofdata_to_platdata()
399 priv->iobase = pdata->iobase; in ftmac100_ofdata_to_platdata()
Drtl8169.c326 ulong iobase; member
587 return rtl_recv_common(dev, priv->iobase, packetp); in rtl8169_eth_recv()
593 dev->iobase, NULL); in rtl_recv()
683 return rtl_send_common(dev, priv->iobase, packet, length); in rtl8169_eth_send()
690 dev->iobase, packet, length); in rtl_send()
891 rtl8169_common_start(dev, plat->enetaddr, priv->iobase); in rtl8169_eth_start()
902 dev->enetaddr, dev->iobase); in rtl_reset()
936 rtl_halt_common(priv->iobase); in rtl8169_eth_stop()
944 rtl_halt_common(dev->iobase); in rtl_halt()
1105 u32 iobase; in rtl8169_initialize() local
[all …]
Dat91_emac.c158 return (at91_emac_t *) netdev->iobase; in get_emacbase_by_name()
190 emac = (at91_emac_t *) netdev->iobase; in at91emac_phy_reset()
225 emac = (at91_emac_t *) netdev->iobase; in at91emac_phy_init()
324 emac = (at91_emac_t *) netdev->iobase; in at91emac_init()
386 emac = (at91_emac_t *) netdev->iobase; in at91emac_halt()
396 emac = (at91_emac_t *) netdev->iobase; in at91emac_send()
416 emac = (at91_emac_t *) netdev->iobase; in at91emac_recv()
454 emac = (at91_emac_t *) netdev->iobase; in at91emac_write_hwaddr()
471 int at91emac_register(bd_t *bis, unsigned long iobase) in at91emac_register() argument
477 if (iobase == 0) in at91emac_register()
[all …]
Drtl8139.c208 u32 iobase; in rtl8139_initialize() local
216 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); in rtl8139_initialize()
217 iobase &= ~0xf; in rtl8139_initialize()
219 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); in rtl8139_initialize()
231 dev->iobase = (int)bus_to_phys(iobase); in rtl8139_initialize()
258 ioaddr = dev->iobase; in rtl8139_probe()
417 ioaddr = dev->iobase; in rtl_transmit()
473 ioaddr = dev->iobase; in rtl_poll()
529 ioaddr = dev->iobase; in rtl_disable()
Dks8851_mll.c110 writew(offset | (BE0 << shift_bit), dev->iobase + 2); in ks_rdreg8()
112 return (u8)(readw(dev->iobase) >> shift_data); in ks_rdreg8()
117 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); in ks_rdreg16()
119 return readw(dev->iobase); in ks_rdreg16()
127 writew(offset | (BE0 << shift_bit), dev->iobase + 2); in ks_wrreg8()
128 writew(value_write, dev->iobase); in ks_wrreg8()
133 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); in ks_wrreg16()
134 writew(val, dev->iobase); in ks_wrreg16()
149 *wptr++ = readw(dev->iobase); in ks_inblk()
163 writew(*wptr++, dev->iobase); in ks_outblk()
[all …]
Dax88180.h358 return le16_to_cpu(readw(addr + (void *)dev->iobase)); in INW()
367 writew(cpu_to_le16(command), addr + (void *)dev->iobase); in OUTW()
372 return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase)); in READ_RXBUF()
377 writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase); in WRITE_TXBUF()
382 writel(cpu_to_le32(command), addr + (void *)dev->iobase); in OUTW()
387 return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase)); in READ_RXBUF()
392 writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase); in WRITE_TXBUF()
Dxilinx_axi_emac.c91 struct axi_regs *iobase; member
190 struct axi_regs *regs = priv->iobase; in phyread()
216 struct axi_regs *regs = priv->iobase; in phywrite()
245 struct axi_regs *regs = priv->iobase; in axiemac_phy_init()
290 struct axi_regs *regs = priv->iobase; in setup_phy()
372 struct axi_regs *regs = priv->iobase; in axi_ethernet_init()
423 struct axi_regs *regs = priv->iobase; in axiemac_write_hwaddr()
462 struct axi_regs *regs = priv->iobase; in axiemac_start()
718 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); in axi_emac_ofdata_to_platdata()
719 priv->iobase = (struct axi_regs *)pdata->iobase; in axi_emac_ofdata_to_platdata()
[all …]
Dnatsemi.c255 return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); in INW()
261 return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); in INL()
267 *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); in OUTW()
273 *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); in OUTL()
295 u32 iobase, status, chip_config; in natsemi_initialize() local
306 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); in natsemi_initialize()
307 iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ in natsemi_initialize()
330 dev->iobase = bus_to_phys(iobase); in natsemi_initialize()
332 printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); in natsemi_initialize()
446 dev->iobase + ee_addr, write_cmd, value);
[all …]
Ddc2114x.c175 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); in INL()
180 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); in OUTL()
199 unsigned int iobase; in dc21x4x_initialize() local
256 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); in dc21x4x_initialize()
257 iobase &= PCI_BASE_ADDRESS_IO_MASK; in dc21x4x_initialize()
260 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); in dc21x4x_initialize()
261 iobase &= PCI_BASE_ADDRESS_MEM_MASK; in dc21x4x_initialize()
263 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); in dc21x4x_initialize()
280 dev->iobase = pci_io_to_phys(devbusfn, iobase); in dc21x4x_initialize()
282 dev->iobase = pci_mem_to_phys(devbusfn, iobase); in dc21x4x_initialize()
Dftgmac100.c47 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_mdiobus_read()
82 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_mdiobus_write()
253 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_update_link_speed()
320 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_reset()
336 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_set_mac()
358 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_halt()
367 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_init()
510 struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; in ftgmac100_send()
565 dev->iobase = CONFIG_FTGMAC100_BASE; in ftgmac100_initialize()
Dcalxedaxgmac.c317 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; in init_rx_desc()
333 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; in init_tx_desc()
341 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_reset()
359 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_hwmacaddr()
369 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_init()
428 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_tx()
456 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_rx()
481 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_halt()
525 dev->iobase = (int)base_addr; in calxedaxgmac_initialize()
Dzynq_gem.c178 struct zynq_gem_regs *iobase; member
192 struct zynq_gem_regs *regs = priv->iobase; in phy_setup_op()
288 struct zynq_gem_regs *regs = priv->iobase; in zynq_gem_setup_mac()
317 struct zynq_gem_regs *regs = priv->iobase; in zynq_phy_init()
364 struct zynq_gem_regs *regs = priv->iobase; in zynq_gem_init()
488 struct zynq_gem_regs *regs = priv->iobase; in zynq_gem_send()
586 struct zynq_gem_regs *regs = priv->iobase; in zynq_gem_halt()
699 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); in zynq_gem_ofdata_to_platdata()
700 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; in zynq_gem_ofdata_to_platdata()
724 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, in zynq_gem_ofdata_to_platdata()
Ddesignware.c575 dev->iobase = (int)base_addr; in designware_initialize()
673 u32 iobase = pdata->iobase; in designware_eth_probe() local
728 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); in designware_eth_probe()
729 iobase &= PCI_BASE_ADDRESS_MEM_MASK; in designware_eth_probe()
730 iobase = dm_pci_mem_to_phys(dev, iobase); in designware_eth_probe()
732 pdata->iobase = iobase; in designware_eth_probe()
737 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); in designware_eth_probe()
738 ioaddr = iobase; in designware_eth_probe()
799 pdata->iobase = dev_read_addr(dev); in designware_eth_ofdata_to_platdata()
Dns8382x.c276 return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); in INW()
282 return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); in INL()
288 *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); in OUTW()
294 *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); in OUTL()
311 u32 iobase, status; in ns8382x_initialize() local
321 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); in ns8382x_initialize()
322 iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */ in ns8382x_initialize()
324 debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase); in ns8382x_initialize()
347 dev->iobase = bus_to_phys(iobase); in ns8382x_initialize()
/external/u-boot/drivers/ata/
Dsata_sil3114.c37 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */ variable
370 u32 port = iobase[5]; in wait_for_irq()
654 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]); in init_sata()
655 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]); in init_sata()
656 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]); in init_sata()
657 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]); in init_sata()
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]); in init_sata()
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]); in init_sata()
661 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) || in init_sata()
662 (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) || in init_sata()
[all …]
/external/u-boot/drivers/misc/
Dsmsc_sio1007.c29 void sio1007_enable_serial(int port, int num, int iobase, int irq) in sio1007_enable_serial() argument
40 sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2); in sio1007_enable_serial()
44 sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2); in sio1007_enable_serial()
52 void sio1007_enable_runtime(int port, int iobase) in sio1007_enable_runtime() argument
58 sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4); in sio1007_enable_runtime()
59 sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12); in sio1007_enable_runtime()
/external/u-boot/arch/x86/lib/
Dpinctrl_ich6.c61 static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) in ich6_pinctrl_cfg_pin() argument
105 if (iobase != -1) { in ich6_pinctrl_cfg_pin()
120 iobase_addr = iobase + pad_offset; in ich6_pinctrl_cfg_pin()
158 u32 iobase = -1; in ich6_pinctrl_probe() local
183 ret = pch_get_io_base(pch, &iobase); in ich6_pinctrl_probe()
185 debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase); in ich6_pinctrl_probe()
193 ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node); in ich6_pinctrl_probe()
/external/u-boot/board/micronas/vct/
Debi_smc911x.c39 addr += dev->iobase; in smc911x_reg_read()
51 addr += dev->iobase; in smc911x_reg_write()
62 addr += dev->iobase; in pkt_data_push()
77 addr += dev->iobase; in pkt_data_pull()
/external/u-boot/drivers/clk/
Dclk_pic32.c87 void __iomem *iobase; member
96 v = readl(priv->iobase + SPLLCON); in pic32_get_pll_rate()
122 v = readl(priv->iobase + OSCCON); in pic32_get_sysclk()
158 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; in pic32_get_pbclk()
193 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_set_refclk()
237 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_get_refclk()
400 priv->iobase = ioremap(addr, size); in pic32_clk_probe()
401 if (!priv->iobase) in pic32_clk_probe()
/external/u-boot/arch/x86/include/asm/
Dpnp_def.h67 static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase) in pnp_set_iobase() argument
69 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); in pnp_set_iobase()
70 pnp_write_config(dev, index + 1, iobase & 0xff); in pnp_set_iobase()

1234