| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | thumb2-mclass.s | 16 mrs r0, ipsr
31 @ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
50 msr ipsr, r0
65 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80]
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-mclass.s | 17 mrs r0, ipsr
29 @ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
49 msr ipsr, r0
73 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumb2-mclass.s | 17 mrs r0, ipsr
29 @ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
49 msr ipsr, r0
73 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
|
| /external/capstone/suite/MC/ARM/ |
| D | thumb2-mclass.s.cs | 6 0xef,0xf3,0x05,0x80 = mrs r0, ipsr
32 0x80,0xf3,0x05,0x88 = msr ipsr, r0
|
| /external/u-boot/arch/arm/mach-rmobile/ |
| D | pfc-r8a7790.h | 135 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) argument
136 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ argument
137 FN_##ipsr, FN_##fn)
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 11 # CHECK: mrs r0, ipsr
74 # CHECK: msr ipsr, r0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 11 # CHECK: mrs r0, ipsr
74 # CHECK: msr ipsr, r0
|
| /external/u-boot/drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 297 #define PINMUX_IPSR_NOGP(ipsr, fn) \ argument
307 #define PINMUX_IPSR_GPSR(ipsr, fn) \ argument
308 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
318 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ argument
341 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ argument
342 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
|
| D | pfc-r8a77995.c | 474 #define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \ argument
475 PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
477 #define PINMUX_IPSR_PHYS(ipsr, fn, msel) \ argument
|
| /external/llvm/test/CodeGen/ARM/ |
| D | special-reg-mcore.ll | 15 ; MCORE: mrs r1, ipsr
75 ; MCORE: msr ipsr, r0
134 !16 = !{!"ipsr"}
|
| D | special-reg-v8m-base.ll | 13 ; CHECK: mrs r1, ipsr
77 ; CHECK: msr ipsr, r0
128 !16 = !{!"ipsr"}
|
| D | special-reg-v8m-main.ll | 13 ; MAINLINE: mrs r1, ipsr
109 ; MAINLINE: msr ipsr, r0
192 !16 = !{!"ipsr"}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | special-reg-v8m-base.ll | 13 ; CHECK: mrs r1, ipsr
77 ; CHECK: msr ipsr, r0
128 !16 = !{!"ipsr"}
|
| D | special-reg-mcore.ll | 15 ; MCORE: mrs r1, ipsr @ encoding: [0xef,0xf3,0x05,0x81]
75 ; MCORE: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
134 !16 = !{!"ipsr"}
|
| D | special-reg-v8m-main.ll | 13 ; MAINLINE: mrs r1, ipsr
106 ; MAINLINE: msr ipsr, r0
187 !16 = !{!"ipsr"}
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSystemRegister.inc | 57 ipsr = 2053,
270 { "ipsr", 0x805, 0x105, 0x805, {} }, // 16
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMSystemRegister.td | 67 def : MClassSysReg<0, 0, 1, 0x805, "ipsr">;
|