| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 439 bool isAdd = true; in EncodeAddrModeOpValues() local
444 isAdd = false; in EncodeAddrModeOpValues()
450 isAdd = false; in EncodeAddrModeOpValues()
454 return isAdd; in EncodeAddrModeOpValues()
705 bool isAdd = true; in getAddrModeImm12OpValue() local
711 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
729 isAdd = false; in getAddrModeImm12OpValue()
734 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); in getAddrModeImm12OpValue()
738 if (isAdd) in getAddrModeImm12OpValue()
759 bool isAdd = Imm8 >= 0; in getT2Imm8s4OpValue() local
[all …]
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| D | ARMAsmBackend.cpp | 218 bool isAdd = true; in adjustFixupValue() local
221 isAdd = false; in adjustFixupValue()
224 Value |= isAdd << 23; in adjustFixupValue()
369 bool isAdd = true; in adjustFixupValue() local
372 isAdd = false; in adjustFixupValue()
377 Value |= isAdd << 23; in adjustFixupValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 571 bool isAdd = true; in EncodeAddrModeOpValues() local
576 isAdd = false; in EncodeAddrModeOpValues()
582 isAdd = false; in EncodeAddrModeOpValues()
586 return isAdd; in EncodeAddrModeOpValues()
890 bool isAdd = true; in getAddrModeImm12OpValue() local
899 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
914 isAdd = false; in getAddrModeImm12OpValue()
917 isAdd = false; in getAddrModeImm12OpValue()
922 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
926 if (isAdd) in getAddrModeImm12OpValue()
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| D | ARMAsmBackend.cpp | 431 bool isAdd = true; in adjustFixupValue() local
434 isAdd = false; in adjustFixupValue()
440 Value |= isAdd << 23; in adjustFixupValue()
660 bool isAdd = true; in adjustFixupValue() local
663 isAdd = false; in adjustFixupValue()
671 return Value | (isAdd << 23); in adjustFixupValue()
680 bool isAdd = true; in adjustFixupValue() local
683 isAdd = false; in adjustFixupValue()
691 Value |= isAdd << 23; in adjustFixupValue()
707 bool isAdd = true; in adjustFixupValue() local
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 560 bool isAdd = true; in EncodeAddrModeOpValues() local
565 isAdd = false; in EncodeAddrModeOpValues()
571 isAdd = false; in EncodeAddrModeOpValues()
575 return isAdd; in EncodeAddrModeOpValues()
879 bool isAdd = true; in getAddrModeImm12OpValue() local
888 isAdd = false ; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
903 isAdd = false; in getAddrModeImm12OpValue()
906 isAdd = false; in getAddrModeImm12OpValue()
911 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
915 if (isAdd) in getAddrModeImm12OpValue()
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| D | ARMAsmBackend.cpp | 410 bool isAdd = true; in adjustFixupValue() local
413 isAdd = false; in adjustFixupValue()
419 Value |= isAdd << 23; in adjustFixupValue()
610 bool isAdd = true; in adjustFixupValue() local
613 isAdd = false; in adjustFixupValue()
621 return Value | (isAdd << 23); in adjustFixupValue()
630 bool isAdd = true; in adjustFixupValue() local
633 isAdd = false; in adjustFixupValue()
641 Value |= isAdd << 23; in adjustFixupValue()
657 bool isAdd = true; in adjustFixupValue() local
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| /external/apache-commons-math/src/main/java/org/apache/commons/math/fraction/ |
| D | Fraction.java | 476 private Fraction addSub(Fraction fraction, boolean isAdd) { in addSub() argument
482 return isAdd ? fraction : fraction.negate(); in addSub()
495 (isAdd ? MathUtils.addAndCheck(uvp, upv) : in addSub()
506 BigInteger t = isAdd ? uvp.add(upv) : uvp.subtract(upv); in addSub()
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| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/util/ |
| D | SyntheticAccessorFSM.java | 555 boolean isAdd = ((mathOp == ADD) && !negativeConstant) || in getIncrementType()
559 if (isAdd) { in getIncrementType()
565 if (isAdd) { in getIncrementType()
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| /external/smali/dexlib2/src/main/ragel/ |
| D | SyntheticAccessorFSM.rl | 252 boolean isAdd = ((mathOp == ADD) && !negativeConstant) ||
256 if (isAdd) {
262 if (isAdd) {
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 342 bool isAdd; member
1220 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
1378 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
1380 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
1389 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
1392 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
1399 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
1407 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
1628 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, in CreatePostIdxReg() argument
1634 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | InstrDocsEmitter.cpp | 111 FLAG(isAdd) in EmitInstrDocs()
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| D | CodeGenInstruction.h | 234 bool isAdd : 1; variable
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| D | InstrInfoEmitter.cpp | 578 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 314 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 247 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 421 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in findInductionRegister() local
423 if (isAdd) { in findInductionRegister()
1602 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in fixupInductionVariable() local
1604 if (isAdd) { in fixupInductionVariable()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 306 bool isAdd = true; in getAddrMode5OpValue() local
309 isAdd = false; in getAddrMode5OpValue()
313 if (isAdd) in getAddrMode5OpValue()
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| D | ARMInstrInfo.td | 2231 // {12} isAdd
2248 // {12} isAdd
2340 // {12} isAdd
2359 // {12} isAdd
2376 // {12} isAdd
2395 // {12} isAdd
2486 // {12} isAdd
2503 // {12} isAdd
2645 // {12} isAdd
2664 // {12} isAdd
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| D | ARMInstrFormats.td | 544 // {12} isAdd
562 // {12} isAdd
583 // {12} isAdd
636 // {8} isAdd
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 758 bool isAdd; member
2457 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2664 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2666 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
2675 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2678 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
2685 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2693 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
3138 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
3142 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 524 bool isAdd; member
2185 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2392 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2394 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
2403 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2406 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
2413 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
2421 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
2826 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2689 // {12} isAdd
2707 // {12} isAdd
2799 // {12} isAdd
2818 // {12} isAdd
2835 // {12} isAdd
2854 // {12} isAdd
2960 // {12} isAdd
2978 // {12} isAdd
3122 // {12} isAdd
3141 // {12} isAdd
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 442 if (DI->getDesc().isAdd()) { in findInductionRegister()
1643 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 2579 // {12} isAdd
2597 // {12} isAdd
2689 // {12} isAdd
2708 // {12} isAdd
2725 // {12} isAdd
2744 // {12} isAdd
2850 // {12} isAdd
2868 // {12} isAdd
3012 // {12} isAdd
3031 // {12} isAdd
[all …]
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| D | ARMInstrFormats.td | 673 // {12} isAdd
691 // {12} isAdd
712 // {12} isAdd
765 // {8} isAdd
|