| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 155 let isAllocatable = 0;
160 let isAllocatable = 0;
218 let isAllocatable = 0;
403 let isAllocatable = 0;
409 let isAllocatable = 0;
444 let isAllocatable = 0;
467 let isAllocatable = 0;
482 let isAllocatable = 0;
497 let isAllocatable = 0;
550 let isAllocatable = 0;
[all …]
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| D | R600RegisterInfo.td | 160 let isAllocatable = 0 in {
206 } // End isAllocatable = 0
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 112 if (!RC || RC->isAllocatable()) in getAllocatableClass()
118 if (SubRC->isAllocatable()) in getAllocatableClass()
149 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
166 if ((*I)->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 40 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
97 assert(RegClass->isAllocatable() && in createVirtualRegister()
455 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
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| D | RegAllocFast.cpp | 536 !RC->contains(Hint) || !MRI->isAllocatable(Hint))) in allocVirtReg()
814 if (MRI->isAllocatable(LI.PhysReg)) in AllocateBasicBlock()
953 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
1040 if (!MRI->isAllocatable(Reg)) continue; in AllocateBasicBlock()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 175 if (!RC || RC->isAllocatable()) in getAllocatableClass()
181 if (SubRC->isAllocatable()) in getAllocatableClass()
211 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
227 if (C->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 60 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
169 assert(RegClass->isAllocatable() && in createVirtualRegister()
525 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
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| D | RegAllocFast.cpp | 555 MRI->isAllocatable(Hint) && RC.contains(Hint)) { in allocVirtReg()
864 if (MRI->isAllocatable(LI.PhysReg)) in allocateBasicBlock()
963 if (!MRI->isAllocatable(Reg)) continue; in allocateBasicBlock()
1045 if (!MRI->isAllocatable(Reg)) continue; in allocateBasicBlock()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 346 let Size = 32, isAllocatable = 0 in
353 let isAllocatable = 0 in
356 let Size = 64, isAllocatable = 0 in
361 let Size = 32, isAllocatable = 0 in
371 let Size = 64, isAllocatable = 0 in
382 let isAllocatable = 0 in
388 let Size = 32, isAllocatable = 0 in
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 120 let isAllocatable = 0;
177 let isAllocatable = 0;
275 let isAllocatable = 0;
291 let isAllocatable = 0;
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| D | SIFrameLowering.cpp | 165 assert(MRI.isAllocatable(Reg)); in emitPrologue()
195 if (!MRI.isAllocatable(Reg) || in emitPrologue()
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| D | R600RegisterInfo.td | 159 let isAllocatable = 0 in {
205 } // End isAllocatable = 0
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterClassInfo.h | 125 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() function
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| D | RegAllocFast.cpp | 489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint))) in allocVirtReg()
765 if (RegClassInfo.isAllocatable(*I)) in AllocateBasicBlock()
896 if (!RegClassInfo.isAllocatable(Reg)) continue; in AllocateBasicBlock()
985 if (!RegClassInfo.isAllocatable(Reg)) continue; in AllocateBasicBlock()
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| D | CalcSpillWeights.cpp | 146 if (hweight > bestPhys && LIS.isAllocatable(hint)) in CalculateWeightAndHint()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 105 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 89 if ((*I)->isAllocatable()) in getAllocatableSet()
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 55 let isAllocatable = 0;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 58 let isAllocatable = 0;
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 58 let isAllocatable = 0;
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 63 let isAllocatable = 0;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 63 let isAllocatable = 0;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 389 let isAllocatable = 0 in
398 let isAllocatable = 0 in
522 let isAllocatable = 0;
547 let isAllocatable = 0;
551 let isAllocatable = 0;
555 let isAllocatable = 0;
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 120 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 104 bool isAllocatable() const { return Allocatable; } in isAllocatable() function
|