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Searched refs:isOperationLegal (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp577 return TLI.isOperationLegal(Opcode, VT); in hasOperation()
703 return TLI.isOperationLegal(ISD::ConstantFP, VT) || in isNegatibleForFree()
1131 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1137 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
2091 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) && in visitADD()
2092 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) && in visitADD()
2176 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
2259 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADDLike()
2546 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
2599 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT)) in visitSUB()
[all …]
DTargetLowering.cpp2203 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
3486 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
3490 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
3565 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
3568 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
DLegalizeIntegerTypes.cpp416 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
DSelectionDAGBuilder.cpp5703 if (X == Y && TLI.isOperationLegal(RotateOpcode, VT)) { in visitIntrinsicCall()
9693 if (!TLI.isOperationLegal(ISD::SHL, PTy)) in findBitTestClusters()
DLegalizeDAG.cpp3915 if (TLI.isOperationLegal(RevRot, ResVT)) { in ExpandNode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp718 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1472 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1550 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { in tryFoldToZero()
2001 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2037 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2060 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { in SimplifyNodeWithTwoResults()
2070 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { in SimplifyNodeWithTwoResults()
2088 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
2099 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
[all …]
DTargetLowering.cpp2111 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
DLegalizeIntegerTypes.cpp359 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
DSelectionDAGBuilder.cpp2265 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) in handleBitTestsSwitchCase()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp988 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
994 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
1726 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && in visitADD()
1760 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
1847 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
2494 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
2530 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
2562 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { in SimplifyNodeWithTwoResults()
2578 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) in SimplifyNodeWithTwoResults()
2588 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) in SimplifyNodeWithTwoResults()
[all …]
DTargetLowering.cpp1606 (isOperationLegal(ISD::SETCC, newVT) && in SimplifySetCC()
2853 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2857 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : in BuildSDIV()
2931 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2934 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : in BuildUDIV()
DLegalizeIntegerTypes.cpp426 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
DSelectionDAGBuilder.cpp8585 if (!TLI.isOperationLegal(ISD::SHL, PTy)) in findBitTestClusters()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h388 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
/external/llvm/include/llvm/Target/
DTargetLowering.h649 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetLowering.h936 bool isOperationLegal(unsigned Op, EVT VT) const { in isOperationLegal() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1900 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
DAMDGPUISelLowering.cpp2912 isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)) { in performShlCombine()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp2009 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp2644 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); in hasDivRemOp()
DX86ISelLowering.cpp6882 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT)) in EltsFromConsecutiveLoads()
17936 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest()
18536 TLI.isOperationLegal(ISD::UMIN, VT)) { in LowerVSETCC()
31216 TLI.isOperationLegal(Opcode, VT)) { in combineShuffle()
34944 DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT)) { in combineLogicBlendIntoPBLENDV()
36555 if (SrcVT.getScalarType() == MVT::i64 && TLI.isOperationLegal(Opcode, VT) && in combineTruncatedArithmetic()
36556 !TLI.isOperationLegal(Opcode, SrcVT)) in combineTruncatedArithmetic()
36563 if (TLI.isOperationLegal(Opcode, VT) && in combineTruncatedArithmetic()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp5663 if (isAfterLegalize && !TLI.isOperationLegal(ISD::LOAD, VT)) in EltsFromConsecutiveLoads()
14832 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest()
26087 TLI.isOperationLegal(Opcode, VT)) { in combineShuffle()
26376 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) { in combineExtractVectorElt()
30507 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT)) in combineUIntToFP()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp4298 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp4587 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp14106 if (VT.isVector() && TLI.isOperationLegal(Opcode, VT) && in stripModuloOnShift()