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Searched refs:isRegSequenceLike (Results 1 – 10 of 10) sorted by relevance

/external/llvm/include/llvm/MC/
DMCInstrDesc.h307 bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); } in isRegSequenceLike() function
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp207 (MI.isRegSequenceLike() || MI.isInsertSubregLike() || in isUncoalescableCopy()
1153 if (MI.isBitcast() || (MI.isRegSequenceLike() || MI.isInsertSubregLike() || in getCopyRewriter()
1716 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
1902 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
DTargetInstrInfo.cpp1127 MI.isRegSequenceLike()) && "Instruction do not have the proper type"); in getRegSequenceInputs()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCInstrDesc.h349 bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); } in isRegSequenceLike() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp250 (MI.isRegSequenceLike() || MI.isInsertSubregLike() || in isUncoalescableCopy()
1087 if (MI.isBitcast() || MI.isRegSequenceLike() || MI.isInsertSubregLike() || in getCopyRewriter()
1871 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
2061 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
DTargetInstrInfo.cpp1157 MI.isRegSequenceLike()) && "Instruction do not have the proper type"); in getRegSequenceInputs()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h565 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstr.h619 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp4599 assert(MI.isRegSequenceLike() && "Invalid kind of instruction"); in getRegSequenceLikeInputs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp4994 assert(MI.isRegSequenceLike() && "Invalid kind of instruction"); in getRegSequenceLikeInputs()