Searched refs:isVGPR (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 69 static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI, in isVGPR() function
96 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
110 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
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| D | GCNHazardRecognizer.cpp | 238 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
256 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
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| D | SIRegisterInfo.h | 193 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
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| D | SIRegisterInfo.cpp | 1005 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, in isVGPR() function in SIRegisterInfo
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 413 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
434 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
544 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
651 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
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| D | SIShrinkInstructions.cpp | 87 if (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg())) in canShrink()
95 if (!Src2->isReg() || !TRI.isVGPR(MRI, Src2->getReg()) || in canShrink()
106 if (Src1 && (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()) || in canShrink()
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| D | SIFixWWMLiveness.cpp | 123 if (TRI->isVGPR(*MRI, Reg)) in addDefs()
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| D | SIInsertWaitcnts.cpp | 492 if (TRI->isVGPR(MRIA, Op.getReg())) { in getRegInterval()
523 assert(TRI->isVGPR(*MRI, Opnd.getReg())); in setExpScore()
585 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) { in updateByEvent()
633 TRI->isVGPR(MRIA, DefMO.getReg())) { in updateByEvent()
641 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) { in updateByEvent()
1068 if (TRI->isVGPR(MRIA, Op.getReg())) { in generateWaitcntInstBefore()
1104 if (TRI->isVGPR(MRIA, Def.getReg())) { in generateWaitcntInstBefore()
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| D | SIRegisterInfo.h | 197 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
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| D | SIInsertSkips.cpp | 248 if (TRI->isVGPR(MBB.getParent()->getRegInfo(), in kill()
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| D | SIPeepholeSDWA.cpp | 1089 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) in legalizeScalarOperands()
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| D | SIInstrInfo.cpp | 1992 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg()); in FoldImmediate()
3276 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
3282 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
3301 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
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| D | SIRegisterInfo.cpp | 1504 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, in isVGPR() function in SIRegisterInfo
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| D | SIISelLowering.cpp | 8481 return TRI.isVGPR(MRI, Reg); in isSDNodeSourceOfDivergence()
8486 if (TRI.isVGPR(MRI, Reg)) in isSDNodeSourceOfDivergence()
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