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Searched refs:isl_format_layouts (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl.h1373 extern const struct isl_format_layout isl_format_layouts[];
1386 return &isl_format_layouts[fmt]; in isl_format_get_layout()
1392 return isl_format_layouts[fmt].name; in isl_format_get_name()
1507 return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB; in isl_format_is_srgb()
1517 return isl_format_layouts[fmt].channels.r.bits > 0 && in isl_format_is_rgb()
1518 isl_format_layouts[fmt].channels.g.bits > 0 && in isl_format_is_rgb()
1519 isl_format_layouts[fmt].channels.b.bits > 0 && in isl_format_is_rgb()
1520 isl_format_layouts[fmt].channels.a.bits == 0; in isl_format_is_rgb()
Disl_storage_image.c315 param->stride[0] = isl_format_layouts[format].bpb / 8; in isl_buffer_fill_image_param()
/external/mesa3d/src/intel/vulkan/
DgenX_pipeline.c39 case 0: bits = isl_format_layouts[format].channels.r.bits; break; in vertex_element_comp_control()
40 case 1: bits = isl_format_layouts[format].channels.g.bits; break; in vertex_element_comp_control()
41 case 2: bits = isl_format_layouts[format].channels.b.bits; break; in vertex_element_comp_control()
42 case 3: bits = isl_format_layouts[format].channels.a.bits; break; in vertex_element_comp_control()
65 !isl_format_layouts[format].channels.b.bits && in vertex_element_comp_control()
66 isl_format_layouts[format].channels.r.type == ISL_RAW) { in vertex_element_comp_control()
72 isl_format_layouts[format].channels.r.type == ISL_RAW) { in vertex_element_comp_control()
76 } else if (isl_format_layouts[format].channels.r.type == ISL_UINT || in vertex_element_comp_control()
77 isl_format_layouts[format].channels.r.type == ISL_SINT) { in vertex_element_comp_control()
Danv_formats.c565 !util_is_power_of_two(isl_format_layouts[base_isl_format].bpb) && in get_image_format_features()
/external/mesa3d/prebuilt-intermediates/isl/
Disl_format_layout.c29 isl_format_layouts[] = { variable