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Searched refs:kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-shadd8-a32.h457 const Inputs kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5[] = { variable
8916 ARRAY_SIZE(kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5),
8917 kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5,
Dsimulator-cond-rd-rn-rm-shadd8-t32.h457 const Inputs kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5[] = { variable
8916 ARRAY_SIZE(kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5),
8917 kOutputs_Shadd8_RdIsRnIsRm_al_r5_r5_r5,