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Searched refs:kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-uadd16-t32.h721 const Inputs kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14[] = { variable
8948 ARRAY_SIZE(kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14),
8949 kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14,
Dsimulator-cond-rd-rn-rm-uadd16-a32.h721 const Inputs kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14[] = { variable
8948 ARRAY_SIZE(kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14),
8949 kOutputs_Uadd16_RdIsRnIsRm_al_r14_r14_r14,