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Searched refs:kOutputs_Uqadd16_Condition_ge_r0_r0_r0 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-uqadd16-a32.h207 const Inputs kOutputs_Uqadd16_Condition_ge_r0_r0_r0[] = { variable
8876 ARRAY_SIZE(kOutputs_Uqadd16_Condition_ge_r0_r0_r0),
8877 kOutputs_Uqadd16_Condition_ge_r0_r0_r0,
Dsimulator-cond-rd-rn-rm-uqadd16-t32.h207 const Inputs kOutputs_Uqadd16_Condition_ge_r0_r0_r0[] = { variable
8876 ARRAY_SIZE(kOutputs_Uqadd16_Condition_ge_r0_r0_r0),
8877 kOutputs_Uqadd16_Condition_ge_r0_r0_r0,