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Searched refs:kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-uqadd16-a32.h4794 const Inputs kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12[] = { variable
9032 ARRAY_SIZE(kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12),
9033 kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12,
Dsimulator-cond-rd-rn-rm-uqadd16-t32.h4794 const Inputs kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12[] = { variable
9032 ARRAY_SIZE(kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12),
9033 kOutputs_Uqadd16_RnIsRm_al_r1_r12_r12,