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Searched refs:kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4 (Results 1 – 2 of 2) sorted by relevance

/external/vixl/test/aarch32/traces/
Dsimulator-cond-rd-rn-rm-usub16-a32.h7824 const Inputs kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4[] = { variable
9092 ARRAY_SIZE(kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4),
9093 kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4,
Dsimulator-cond-rd-rn-rm-usub16-t32.h7824 const Inputs kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4[] = { variable
9092 ARRAY_SIZE(kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4),
9093 kOutputs_Usub16_RdIsNotRnIsNotRm_al_r10_r8_r4,