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Searched refs:lane0 (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-addp.ll7 %lane0.i = extractelement <2 x double> %a, i32 0
9 %vpaddd.i = fadd double %lane0.i, %lane1.i
18 %lane0.i = extractelement <2 x i64> %a, i32 0
20 %vpaddd.i = add i64 %lane0.i, %lane1.i
28 %lane0.i = extractelement <2 x float> %a, i32 0
30 %vpaddd.i = fadd float %lane0.i, %lane1.i
/external/llvm/test/CodeGen/AArch64/
Darm64-addp.ll7 %lane0.i = extractelement <2 x double> %a, i32 0
9 %vpaddd.i = fadd double %lane0.i, %lane1.i
18 %lane0.i = extractelement <2 x i64> %a, i32 0
20 %vpaddd.i = add i64 %lane0.i, %lane1.i
28 %lane0.i = extractelement <2 x float> %a, i32 0
30 %vpaddd.i = fadd float %lane0.i, %lane1.i
/external/eigen/Eigen/src/Core/arch/AVX512/
DPacketMath.h464 Packet8f lane0 = _mm256_broadcast_ps((const __m128*)(const void*)from);
466 lane0 = _mm256_blend_ps(
467 lane0, _mm256_castps128_ps256(_mm_permute_ps(
468 _mm256_castps256_ps128(lane0), _MM_SHUFFLE(1, 0, 1, 0))),
472 lane0 = _mm256_permute_ps(lane0, _MM_SHUFFLE(3, 3, 2, 2));
486 return _mm512_insertf32x8(res, lane0, 0);
491 res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane0, 0), 0);
492 res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane0, 1), 1);
502 Packet4d lane0 = _mm256_broadcast_pd((const __m128d*)(const void*)from);
503 lane0 = _mm256_permute_pd(lane0, 3 << 2);
[all …]
/external/v8/src/compiler/
Dinstruction-selector.h668 uint8_t lane0[kBytesPerLane]; in TryMatchDup() local
669 lane0[0] = shuffle[0]; in TryMatchDup()
670 if (lane0[0] % kBytesPerLane != 0) return false; in TryMatchDup()
672 lane0[i] = shuffle[i]; in TryMatchDup()
673 if (lane0[i] != lane0[0] + i) return false; in TryMatchDup()
678 if (lane0[j] != shuffle[i * kBytesPerLane + j]) return false; in TryMatchDup()
681 *index = lane0[0] / kBytesPerLane; in TryMatchDup()
/external/libvpx/libvpx/vp9/common/arm/neon/
Dvp9_highbd_iht16x16_add_neon.c72 #define highbd_iadst_butterfly(in0, in1, c, lane0, lane1, s0, s1) \ argument
74 vmull_lane_s32_dual(in0, c, lane0, s0); \
77 vmlsl_lane_s32_dual(in1, c, lane0, s1); \
/external/u-boot/arch/arm/dts/
Dzynqmp-zc1232-revA.dts82 phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
Dzynqmp.dtsi677 lane0: lane0 { label