Home
last modified time | relevance | path

Searched refs:lane_cnt (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/board/gdsys/common/
Ddp501.c54 u8 lane_cnt; in dp501_link_training() local
68 lane_cnt = 4; in dp501_link_training()
70 lane_cnt = max_lane_cnt; in dp501_link_training()
71 if (lane_cnt != max_lane_cnt) in dp501_link_training()
73 max_lane_cnt, lane_cnt); in dp501_link_training()
74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
/external/u-boot/drivers/video/exynos/
Dexynos_dp.c176 unsigned char lane_cnt[16]; in exynos_dp_handle_edid() local
180 memset(lane_cnt, 0, 16); in exynos_dp_handle_edid()
229 priv->lane_cnt = temp; in exynos_dp_handle_edid()
281 exynos_dp_set_lane_count(regs, priv->lane_cnt); in exynos_dp_link_start()
285 buf[1] = priv->lane_cnt; in exynos_dp_link_start()
294 priv->lane_cnt); in exynos_dp_link_start()
402 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_read_dpcd_lane_stat()
508 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()
543 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()
627 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_equalizer_training()
[all …]
/external/u-boot/arch/arm/mach-exynos/include/mach/
Ddp_info.h70 unsigned char lane_cnt; member