| /external/u-boot/drivers/video/tegra124/ |
| D | dp.c | 431 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()
456 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
462 if (cfg->lane_count == 1) { in _tegra_dp_lower_link_config()
464 cfg->lane_count = cfg->max_lane_count; in _tegra_dp_lower_link_config()
466 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
474 return (cfg->lane_count > 0) ? 0 : -ENOLINK; in _tegra_dp_lower_link_config()
507 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
512 (u64)link_rate * 8 * link_cfg->lane_count) in tegra_dc_dp_calc_config()
520 do_div(ratio_f, link_rate * link_cfg->lane_count); in tegra_dc_dp_calc_config()
600 (8 * link_cfg->lane_count); in tegra_dc_dp_calc_config()
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| D | sor.c | 212 u32 lane_count, int pu) in tegra_dc_sor_power_dplanes() argument
220 switch (lane_count) { in tegra_dc_sor_power_dplanes()
231 debug("dp: invalid lane number %d\n", lane_count); in tegra_dc_sor_power_dplanes()
236 tegra_dc_sor_set_lane_count(dev, lane_count); in tegra_dc_sor_power_dplanes()
387 u8 *lane_count) in tegra_dc_sor_read_link_config() argument
400 *lane_count = 0; in tegra_dc_sor_read_link_config()
403 *lane_count = 1; in tegra_dc_sor_read_link_config()
406 *lane_count = 2; in tegra_dc_sor_read_link_config()
409 *lane_count = 4; in tegra_dc_sor_read_link_config()
425 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) in tegra_dc_sor_set_lane_count() argument
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| D | sor.h | 854 u8 lane_count; member
884 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count);
889 u8 *lane_count);
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| /external/u-boot/drivers/video/rockchip/ |
| D | rk_edp.c | 326 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
337 for (i = 0; i < edp->link_train.lane_count; i++) in rk_edp_set_link_training()
362 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count) in rk_edp_clock_recovery() argument
367 for (lane = 0; lane < lane_count; lane++) { in rk_edp_clock_recovery()
376 static int rk_edp_channel_eq(const u8 *link_status, int lane_count) in rk_edp_channel_eq() argument
386 for (lane = 0; lane < lane_count; lane++) { in rk_edp_channel_eq()
418 static void edp_get_adjust_train(const u8 *link_status, int lane_count, in edp_get_adjust_train() argument
425 for (lane = 0; lane < lane_count; lane++) { in edp_get_adjust_train()
484 edp->link_train.lane_count); in rk_edp_link_train_cr()
497 edp->link_train.lane_count); in rk_edp_link_train_cr()
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 225 uint32_t lane_count = kDRegSizeInBits / kSRegSizeInBits; in GetLane() local
226 VIXL_ASSERT(lane < lane_count); in GetLane()
227 VIXL_ASSERT(GetCode() * lane_count < kNumberOfSRegisters); in GetLane()
228 return SRegister(GetCode() * lane_count + lane); in GetLane()
370 uint32_t lane_count = kQRegSizeInBits / kDRegSizeInBits; in GetDLane() local
371 VIXL_ASSERT(lane < lane_count); in GetDLane()
372 return DRegister(GetCode() * lane_count + lane); in GetDLane()
377 uint32_t lane_count = kQRegSizeInBits / kSRegSizeInBits; in GetSLane() local
378 VIXL_ASSERT(lane < lane_count); in GetSLane()
379 VIXL_ASSERT(GetCode() * lane_count < kNumberOfSRegisters); in GetSLane()
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| /external/v8/src/arm64/ |
| D | simulator-logic-arm64.cc | 954 int lane_count = LaneCountFromFormat(vform); in pmull2() local
955 for (int i = 0; i < lane_count; i++) { in pmull2()
957 PolynomialMult(src1.Uint(vform_src, lane_count + i), in pmull2()
958 src2.Uint(vform_src, lane_count + i))); in pmull2()
1936 int lane_count = LaneCountFromFormat(vform); in addlp() local
1937 for (int i = 0; i < lane_count; i++) { in addlp()
1947 for (int i = 0; i < lane_count; ++i) { in addlp()
2088 int lane_count = LaneCountFromFormat(vform); in uxtl2() local
2091 for (int i = 0; i < lane_count; i++) { in uxtl2()
2092 dst.SetUint(vform, i, src.Uint(vform_half, lane_count + i)); in uxtl2()
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| D | assembler-arm64.h | 289 template <int code, int size, int lane_count = 1>
291 static_assert(IsValidLaneCount(lane_count), "Invalid lane count"); in Create()
292 return VRegister(CPURegister::Create<code, size, kVRegister>(), lane_count); in Create()
295 static VRegister Create(int code, int size, int lane_count = 1) {
296 DCHECK(IsValidLaneCount(lane_count));
298 lane_count);
393 constexpr explicit VRegister(const CPURegister& r, int lane_count) in VRegister() argument
394 : CPURegister(r), lane_count_(lane_count) {} in VRegister()
396 static constexpr bool IsValidLaneCount(int lane_count) { in IsValidLaneCount() argument
397 return base::bits::IsPowerOfTwo(lane_count) && lane_count <= 16; in IsValidLaneCount()
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| D | simulator-arm64.cc | 1190 int lane_count, int rightmost_lane) { in PrintVRegisterFPHelper() argument
1194 unsigned msb = (lane_count + rightmost_lane) * lane_size_in_bytes; in PrintVRegisterFPHelper()
1203 if ((lane_count == 1) && (rightmost_lane == 0)) { in PrintVRegisterFPHelper()
1218 int leftmost_lane = rightmost_lane + lane_count - 1; in PrintVRegisterFPHelper()
1310 int lane_count = 1 << (reg_size_log2 - lane_size_log2); in PrintVRegister() local
1322 PrintVRegisterFPHelper(code, lane_size, lane_count); in PrintVRegister()
1405 int lane_count = GetPrintRegLaneCount(format); in PrintVWrite() local
1410 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane); in PrintVWrite()
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| D | simulator-arm64.h | 1269 int lane_count = 1, int rightmost_lane = 0);
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| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 987 int lane_count = LaneCountFromFormat(vform); in pmull2() local
988 for (int i = 0; i < lane_count; i++) { in pmull2()
991 PolynomialMult(src1.Uint(vform_src, lane_count + i), in pmull2()
992 src2.Uint(vform_src, lane_count + i))); in pmull2()
2163 int lane_count = LaneCountFromFormat(vform); in addlp() local
2164 for (int i = 0; i < lane_count; i++) { in addlp()
2174 for (int i = 0; i < lane_count; ++i) { in addlp()
2547 int lane_count = LaneCountFromFormat(vform); in uxtl2() local
2550 for (int i = 0; i < lane_count; i++) { in uxtl2()
2551 dst.SetUint(vform, i, src.Uint(vform_half, lane_count + i)); in uxtl2()
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| D | simulator-aarch64.cc | 792 int lane_count, in PrintVRegisterFPHelper() argument
798 unsigned msb = ((lane_count + rightmost_lane) * lane_size_in_bytes); in PrintVRegisterFPHelper()
812 if ((lane_count == 1) && (rightmost_lane == 0)) { in PrintVRegisterFPHelper()
839 int leftmost_lane = rightmost_lane + lane_count - 1; in PrintVRegisterFPHelper()
893 int lane_count = 1 << (reg_size_log2 - lane_size_log2); in PrintVRegister() local
905 PrintVRegisterFPHelper(code, lane_size, lane_count); in PrintVRegister()
1017 int lane_count = GetPrintRegLaneCount(format); in PrintVWrite() local
1022 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane); in PrintVWrite()
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| D | simulator-aarch64.h | 1535 int lane_count = 1,
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| /external/gemmlowp/meta/generators/ |
| D | mul_Nx8_Mx8_neon.py | 33 def GenerateMulLanes(registers, lane_count, address): argument
35 for unused_i in range(0, lane_count):
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | edp_rk3288.h | 632 u8 lane_count; member
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| /external/v8/src/compiler/ |
| D | machine-operator.cc | 1341 #define SIMD_LANE_OPS(Type, lane_count) \ argument
1344 DCHECK(0 <= lane_index && lane_index < lane_count); \
1351 DCHECK(0 <= lane_index && lane_index < lane_count); \
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