/external/llvm/test/MC/Mips/ |
D | mips-expansions.s | 144 # CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01] 148 # CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90] 154 # CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03] 158 # CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90] 165 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] 170 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 176 # CHECK-BE: lbu $8, -32767($zero) # encoding: [0x90,0x08,0x80,0x01] 180 # CHECK-LE: lbu $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x90] 187 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] 192 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] [all …]
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D | mips64-expansions.s | 104 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 105 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 116 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 117 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 127 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 128 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 139 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 140 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 151 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 152 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] [all …]
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D | mips-memory-instructions.s | 28 # CHECK: lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90] 38 lbu $4, 4($5)
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D | micromips-loadstore-instructions.s | 13 # CHECK-EL: lbu $6, 8($4) # encoding: [0xc4,0x14,0x08,0x00] 59 # CHECK-EB: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08] 102 lbu $6, 8($4)
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
D | mips-expansions.s | 25 lbu $4, 0x8000 27 # CHECK-LE: lbu $4, -32768($4) # encoding: [0x00,0x80,0x84,0x90] 29 lbu $4, 0x20004($3) 32 # CHECK-LE: lbu $4, 4($4) # encoding: [0x04,0x00,0x84,0x90] 180 # CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01] 184 # CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90] 190 # CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03] 194 # CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90] 201 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01] 206 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] [all …]
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D | mips64-expansions.s | 104 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 105 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 116 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 117 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 127 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 128 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 139 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 140 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] 151 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90] 152 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] [all …]
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D | mips-memory-instructions.s | 28 # CHECK: lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90] 38 lbu $4, 4($5)
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D | micromips-loadstore-instructions.s | 13 # CHECK-EL: lbu $6, 8($4) # encoding: [0xc4,0x14,0x08,0x00] 72 # CHECK-EB: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08] 128 lbu $6, 8($4)
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/external/llvm/test/CodeGen/Mips/ |
D | unalignedload.ll | 20 ; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]]) 21 ; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]]) 25 ; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]]) 26 ; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]]) 45 ; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]]) 46 ; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]]) 47 ; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]]) 55 ; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]]) 56 ; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]]) 57 ; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]]) [all …]
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D | load-store-left-right.ll | 255 ; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 257 ; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 271 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 273 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 275 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 277 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) 288 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 290 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 292 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 294 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
D | unalignedload.ll | 20 ; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]]) 21 ; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]]) 25 ; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]]) 26 ; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]]) 45 ; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]]) 46 ; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]]) 47 ; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]]) 55 ; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]]) 56 ; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]]) 57 ; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]]) [all …]
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D | load-store-left-right.ll | 299 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 301 ; MIPS32-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]]) 307 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 309 ; MIPS64-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]]) 332 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 334 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 336 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 338 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) 370 ; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 372 ; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) [all …]
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/external/libjpeg-turbo/simd/mips/ |
D | jsimd_dspr2.S | 63 lbu t3, 0(t2) 69 lbu t3, 0(t2) 74 lbu t4, 0(t4) 75 lbu t7, 0(t7) 76 lbu t8, 0(t8) 105 lbu t3, 0(t2) 110 lbu t4, 0(t4) 111 lbu t7, 0(t7) 112 lbu t8, 0(t8) 150 lbu \r, \r_offs(\inptr) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | loadstoreconv.ll | 39 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 59 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 80 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 137 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 151 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 170 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 172 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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D | logopm.ll | 39 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 40 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 61 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 85 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 110 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 111 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 132 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 154 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 179 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 180 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) [all …]
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/external/llvm/test/CodeGen/Mips/Fast-ISel/ |
D | loadstoreconv.ll | 39 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 59 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 80 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 137 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 151 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 170 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) 172 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
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D | logopm.ll | 39 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 40 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 61 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 85 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 110 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 111 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) 132 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 154 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 179 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) 180 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
D | mem.ll | 47 define i32 @lbu(i8 *%a) nounwind { 48 ; RV32I-LABEL: lbu: 50 ; RV32I-NEXT: lbu a1, 0(a0) 51 ; RV32I-NEXT: lbu a0, 4(a0) 122 ; RV32I-NEXT: lbu a1, 1(a0) 123 ; RV32I-NEXT: lbu a0, 2(a0) 144 ; RV32I-NEXT: lbu a1, 1(a0) 145 ; RV32I-NEXT: lbu a0, 2(a0)
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D | zext-with-load-is-free.ll | 5 ; TODO: lbu and lhu should be selected to avoid the unnecessary masking. 13 ; RV32I-NEXT: lbu a1, %lo(bytes)(a0) 18 ; RV32I-NEXT: lbu a0, 1(a0)
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/ |
D | vector.ll | 63 ; MIPS32R5EB-NEXT: lbu $1, 37($sp) 65 ; MIPS32R5EB-NEXT: lbu $1, 36($sp) 67 ; MIPS32R5EB-NEXT: lbu $1, 40($sp) 68 ; MIPS32R5EB-NEXT: lbu $2, 41($sp) 95 ; MIPS64R5EB-NEXT: lbu $1, 89($sp) 97 ; MIPS64R5EB-NEXT: lbu $1, 88($sp) 103 ; MIPS64R5EB-NEXT: lbu $3, 81($sp) 105 ; MIPS64R5EB-NEXT: lbu $3, 80($sp) 168 ; MIPS32R5EL-NEXT: lbu $1, 37($sp) 170 ; MIPS32R5EL-NEXT: lbu $1, 36($sp) [all …]
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D | return.ll | 33 ; O32-DAG: lbu $2, %lo(byte)([[R1]]) 35 ; N32-DAG: lbu $2, %lo(byte)([[R1]]) 37 ; N64-DAG: lbu $2, %lo(byte)([[R1]])
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/external/llvm/test/CodeGen/Mips/cconv/ |
D | return.ll | 33 ; O32-DAG: lbu $2, %lo(byte)([[R1]]) 35 ; N32-DAG: lbu $2, %lo(byte)([[R1]]) 37 ; N64-DAG: lbu $2, 0([[R1]])
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/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
D | unalignedload.ll | 15 ; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]]) 27 ; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
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/external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
D | mblaze_memory.s | 9 # CHECK: lbu 12 lbu r1, r2, r3
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/external/capstone/suite/MC/Mips/ |
D | micromips-loadstore-instructions.s.cs | 3 0xc4,0x14,0x08,0x00 = lbu $6, 8($4)
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