| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s | 8 ld1r { v0.16b }, [x0]
9 ld1r { v15.8h }, [x15]
10 ld1r { v31.4s }, [sp]
11 ld1r { v0.2d }, [x0]
12 ld1r { v0.8b }, [x0]
13 ld1r { v15.4h }, [x15]
14 ld1r { v31.2s }, [sp]
15 ld1r { v0.1d }, [x0]
169 ld1r { v0.16b }, [x0], #1
170 ld1r { v15.8h }, [x15], #2
[all …]
|
| D | arm64-simd-ldst.s | 850 ld1r: label
851 ld1r.8b {v4}, [x2]
852 ld1r.8b {v4}, [x2], x3
853 ld1r.16b {v4}, [x2]
854 ld1r.16b {v4}, [x2], x3
855 ld1r.4h {v4}, [x2]
856 ld1r.4h {v4}, [x2], x3
857 ld1r.8h {v4}, [x2]
858 ld1r.8h {v4}, [x2], x3
859 ld1r.2s {v4}, [x2]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s | 8 ld1r { v0.16b }, [x0]
9 ld1r { v15.8h }, [x15]
10 ld1r { v31.4s }, [sp]
11 ld1r { v0.2d }, [x0]
12 ld1r { v0.8b }, [x0]
13 ld1r { v15.4h }, [x15]
14 ld1r { v31.2s }, [sp]
15 ld1r { v0.1d }, [x0]
169 ld1r { v0.16b }, [x0], #1
170 ld1r { v15.8h }, [x15], #2
[all …]
|
| D | arm64-simd-ldst.s | 850 ld1r: label
851 ld1r.8b {v4}, [x2]
852 ld1r.8b {v4}, [x2], x3
853 ld1r.16b {v4}, [x2]
854 ld1r.16b {v4}, [x2], x3
855 ld1r.4h {v4}, [x2]
856 ld1r.4h {v4}, [x2], x3
857 ld1r.8h {v4}, [x2]
858 ld1r.8h {v4}, [x2], x3
859 ld1r.2s {v4}, [x2]
[all …]
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-simd-ldst-one-elem.s.cs | 2 0x00,0xc0,0x40,0x4d = ld1r {v0.16b}, [x0]
3 0xef,0xc5,0x40,0x4d = ld1r {v15.8h}, [x15]
4 0xff,0xcb,0x40,0x4d = ld1r {v31.4s}, [sp]
5 0x00,0xcc,0x40,0x4d = ld1r {v0.2d}, [x0]
6 0x00,0xc0,0x40,0x0d = ld1r {v0.8b}, [x0]
7 0xef,0xc5,0x40,0x0d = ld1r {v15.4h}, [x15]
8 0xff,0xcb,0x40,0x0d = ld1r {v31.2s}, [sp]
9 0x00,0xcc,0x40,0x0d = ld1r {v0.1d}, [x0]
66 0x00,0xc0,0xdf,0x4d = ld1r {v0.16b}, [x0], #1
67 0xef,0xc5,0xdf,0x4d = ld1r {v15.8h}, [x15], #2
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-ldst-one.ll | 127 ; CHECK: ld1r {{{ ?v[0-9]+.16b ?}}}, [x0]
137 ; CHECK: ld1r {{{ ?v[0-9]+.8h ?}}}, [x0]
147 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
157 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
167 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
177 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
187 ; CHECK: ld1r {{{ ?v[0-9]+.8b ?}}}, [x0]
197 ; CHECK: ld1r {{{ ?v[0-9]+.4h ?}}}, [x0]
207 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
226 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
|
| D | arm64-ld1.ll | 450 ; CHECK: ld1r.8b { v0 }, [x0]
467 ; CHECK: ld1r.16b { v0 }, [x0]
492 ; CHECK: ld1r.4h { v0 }, [x0]
505 ; CHECK: ld1r.8h { v0 }, [x0]
522 ; CHECK: ld1r.2s { v0 }, [x0]
533 ; CHECK: ld1r.4s { v0 }, [x0]
546 ; CHECK: ld1r.2d { v0 }, [x0]
912 ; Add rdar://13098923 test case: vld1_dup_u32 doesn't generate ld1r.2s
916 ; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
917 ; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
[all …]
|
| D | fp16-vector-load-store.ll | 24 ; CHECK: ld1r { v0.4h }, [x0]
35 ; CHECK: ld1r { v0.8h }, [x0]
|
| D | arm64-indexed-vector-ldst.ll | 5694 ; CHECK: ld1r.16b { v0 }, [x0], #1
5719 ; CHECK: ld1r.16b { v0 }, [x0], x{{[0-9]+}}
5744 ; CHECK: ld1r.8b { v0 }, [x0], #1
5761 ; CHECK: ld1r.8b { v0 }, [x0], x{{[0-9]+}}
5778 ; CHECK: ld1r.8h { v0 }, [x0], #2
5795 ; CHECK: ld1r.8h { v0 }, [x0], x{{[0-9]+}}
5812 ; CHECK: ld1r.4h { v0 }, [x0], #2
5825 ; CHECK: ld1r.4h { v0 }, [x0], x{{[0-9]+}}
5838 ; CHECK: ld1r.4s { v0 }, [x0], #4
5851 ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-ldst-one.ll | 127 ; CHECK: ld1r {{{ ?v[0-9]+.16b ?}}}, [x0]
137 ; CHECK: ld1r {{{ ?v[0-9]+.8h ?}}}, [x0]
147 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
157 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
167 ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0]
177 ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0]
187 ; CHECK: ld1r {{{ ?v[0-9]+.8b ?}}}, [x0]
197 ; CHECK: ld1r {{{ ?v[0-9]+.4h ?}}}, [x0]
207 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
226 ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0]
|
| D | arm64-ld1.ll | 450 ; CHECK: ld1r.8b { v0 }, [x0]
467 ; CHECK: ld1r.16b { v0 }, [x0]
492 ; CHECK: ld1r.4h { v0 }, [x0]
505 ; CHECK: ld1r.8h { v0 }, [x0]
522 ; CHECK: ld1r.2s { v0 }, [x0]
533 ; CHECK: ld1r.4s { v0 }, [x0]
546 ; CHECK: ld1r.2d { v0 }, [x0]
912 ; Add rdar://13098923 test case: vld1_dup_u32 doesn't generate ld1r.2s
916 ; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
917 ; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
[all …]
|
| D | fp16-vector-load-store.ll | 24 ; CHECK: ld1r { v0.4h }, [x0]
35 ; CHECK: ld1r { v0.8h }, [x0]
|
| D | arm64-indexed-vector-ldst.ll | 5694 ; CHECK: ld1r.16b { v0 }, [x0], #1
5719 ; CHECK: ld1r.16b { v0 }, [x0], x{{[0-9]+}}
5744 ; CHECK: ld1r.8b { v0 }, [x0], #1
5761 ; CHECK: ld1r.8b { v0 }, [x0], x{{[0-9]+}}
5778 ; CHECK: ld1r.8h { v0 }, [x0], #2
5795 ; CHECK: ld1r.8h { v0 }, [x0], x{{[0-9]+}}
5812 ; CHECK: ld1r.4h { v0 }, [x0], #2
5825 ; CHECK: ld1r.4h { v0 }, [x0], x{{[0-9]+}}
5838 ; CHECK: ld1r.4s { v0 }, [x0], #4
5851 ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 924 # CHECK: ld1r.8b { v1 }, [x1]
925 # CHECK: ld1r.8b { v1 }, [x1], x2
926 # CHECK: ld1r.4h { v4 }, [x3]
927 # CHECK: ld1r.4h { v4 }, [x3], x5
928 # CHECK: ld1r.2s { v9 }, [x5]
929 # CHECK: ld1r.2s { v9 }, [x5], x6
930 # CHECK: ld1r.1d { v12 }, [x7]
931 # CHECK: ld1r.1d { v12 }, [x7], x8
938 # CHECK: ld1r.8b { v1 }, [x1], #1
939 # CHECK: ld1r.4h { v1 }, [x1], #2
[all …]
|
| D | neon-instructions.txt | 2082 # CHECK: ld1r { v0.16b }, [x0]
2083 # CHECK: ld1r { v15.8h }, [x15]
2124 # CHECK: ld1r { v0.16b }, [x0], #1
2125 # CHECK: ld1r { v15.8h }, [x15], #2
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 924 # CHECK: ld1r.8b { v1 }, [x1]
925 # CHECK: ld1r.8b { v1 }, [x1], x2
926 # CHECK: ld1r.4h { v4 }, [x3]
927 # CHECK: ld1r.4h { v4 }, [x3], x5
928 # CHECK: ld1r.2s { v9 }, [x5]
929 # CHECK: ld1r.2s { v9 }, [x5], x6
930 # CHECK: ld1r.1d { v12 }, [x7]
931 # CHECK: ld1r.1d { v12 }, [x7], x8
938 # CHECK: ld1r.8b { v1 }, [x1], #1
939 # CHECK: ld1r.4h { v1 }, [x1], #2
[all …]
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 805 0x~~~~~~~~~~~~~~~~ 4d40c002 ld1r {v2.16b}, [x0]
806 0x~~~~~~~~~~~~~~~~ 4dc2c022 ld1r {v2.16b}, [x1], x2
807 0x~~~~~~~~~~~~~~~~ 4ddfc036 ld1r {v22.16b}, [x1], #1
808 0x~~~~~~~~~~~~~~~~ 0d40cc19 ld1r {v25.1d}, [x0]
809 0x~~~~~~~~~~~~~~~~ 0dc2cc29 ld1r {v9.1d}, [x1], x2
810 0x~~~~~~~~~~~~~~~~ 0ddfcc37 ld1r {v23.1d}, [x1], #8
811 0x~~~~~~~~~~~~~~~~ 4d40cc13 ld1r {v19.2d}, [x0]
812 0x~~~~~~~~~~~~~~~~ 4dc2cc35 ld1r {v21.2d}, [x1], x2
813 0x~~~~~~~~~~~~~~~~ 4ddfcc3e ld1r {v30.2d}, [x1], #8
814 0x~~~~~~~~~~~~~~~~ 0d40c818 ld1r {v24.2s}, [x0]
[all …]
|
| D | log-disasm | 805 0x~~~~~~~~~~~~~~~~ 4d40c002 ld1r {v2.16b}, [x0]
806 0x~~~~~~~~~~~~~~~~ 4dc2c022 ld1r {v2.16b}, [x1], x2
807 0x~~~~~~~~~~~~~~~~ 4ddfc036 ld1r {v22.16b}, [x1], #1
808 0x~~~~~~~~~~~~~~~~ 0d40cc19 ld1r {v25.1d}, [x0]
809 0x~~~~~~~~~~~~~~~~ 0dc2cc29 ld1r {v9.1d}, [x1], x2
810 0x~~~~~~~~~~~~~~~~ 0ddfcc37 ld1r {v23.1d}, [x1], #8
811 0x~~~~~~~~~~~~~~~~ 4d40cc13 ld1r {v19.2d}, [x0]
812 0x~~~~~~~~~~~~~~~~ 4dc2cc35 ld1r {v21.2d}, [x1], x2
813 0x~~~~~~~~~~~~~~~~ 4ddfcc3e ld1r {v30.2d}, [x1], #8
814 0x~~~~~~~~~~~~~~~~ 0d40c818 ld1r {v24.2s}, [x0]
[all …]
|
| D | log-cpufeatures-custom | 804 0x~~~~~~~~~~~~~~~~ 4d40c002 ld1r {v2.16b}, [x0] ### {NEON} ###
805 0x~~~~~~~~~~~~~~~~ 4dc2c022 ld1r {v2.16b}, [x1], x2 ### {NEON} ###
806 0x~~~~~~~~~~~~~~~~ 4ddfc036 ld1r {v22.16b}, [x1], #1 ### {NEON} ###
807 0x~~~~~~~~~~~~~~~~ 0d40cc19 ld1r {v25.1d}, [x0] ### {NEON} ###
808 0x~~~~~~~~~~~~~~~~ 0dc2cc29 ld1r {v9.1d}, [x1], x2 ### {NEON} ###
809 0x~~~~~~~~~~~~~~~~ 0ddfcc37 ld1r {v23.1d}, [x1], #8 ### {NEON} ###
810 0x~~~~~~~~~~~~~~~~ 4d40cc13 ld1r {v19.2d}, [x0] ### {NEON} ###
811 0x~~~~~~~~~~~~~~~~ 4dc2cc35 ld1r {v21.2d}, [x1], x2 ### {NEON} ###
812 0x~~~~~~~~~~~~~~~~ 4ddfcc3e ld1r {v30.2d}, [x1], #8 ### {NEON} ###
813 0x~~~~~~~~~~~~~~~~ 0d40c818 ld1r {v24.2s}, [x0] ### {NEON} ###
[all …]
|
| D | log-cpufeatures | 804 0x~~~~~~~~~~~~~~~~ 4d40c002 ld1r {v2.16b}, [x0] // Needs: NEON
805 0x~~~~~~~~~~~~~~~~ 4dc2c022 ld1r {v2.16b}, [x1], x2 // Needs: NEON
806 0x~~~~~~~~~~~~~~~~ 4ddfc036 ld1r {v22.16b}, [x1], #1 // Needs: NEON
807 0x~~~~~~~~~~~~~~~~ 0d40cc19 ld1r {v25.1d}, [x0] // Needs: NEON
808 0x~~~~~~~~~~~~~~~~ 0dc2cc29 ld1r {v9.1d}, [x1], x2 // Needs: NEON
809 0x~~~~~~~~~~~~~~~~ 0ddfcc37 ld1r {v23.1d}, [x1], #8 // Needs: NEON
810 0x~~~~~~~~~~~~~~~~ 4d40cc13 ld1r {v19.2d}, [x0] // Needs: NEON
811 0x~~~~~~~~~~~~~~~~ 4dc2cc35 ld1r {v21.2d}, [x1], x2 // Needs: NEON
812 0x~~~~~~~~~~~~~~~~ 4ddfcc3e ld1r {v30.2d}, [x1], #8 // Needs: NEON
813 0x~~~~~~~~~~~~~~~~ 0d40c818 ld1r {v24.2s}, [x0] // Needs: NEON
[all …]
|
| D | log-cpufeatures-colour | 804 0x~~~~~~~~~~~~~~~~ 4d40c002 ld1r {v2.16b}, [x0] [1;35mNEON[0;m
805 0x~~~~~~~~~~~~~~~~ 4dc2c022 ld1r {v2.16b}, [x1], x2 [1;35mNEON[0;m
806 0x~~~~~~~~~~~~~~~~ 4ddfc036 ld1r {v22.16b}, [x1], #1 [1;35mNEON[0;m
807 0x~~~~~~~~~~~~~~~~ 0d40cc19 ld1r {v25.1d}, [x0] [1;35mNEON[0;m
808 0x~~~~~~~~~~~~~~~~ 0dc2cc29 ld1r {v9.1d}, [x1], x2 [1;35mNEON[0;m
809 0x~~~~~~~~~~~~~~~~ 0ddfcc37 ld1r {v23.1d}, [x1], #8 [1;35mNEON[0;m
810 0x~~~~~~~~~~~~~~~~ 4d40cc13 ld1r {v19.2d}, [x0] [1;35mNEON[0;m
811 0x~~~~~~~~~~~~~~~~ 4dc2cc35 ld1r {v21.2d}, [x1], x2 [1;35mNEON[0;m
812 0x~~~~~~~~~~~~~~~~ 4ddfcc3e ld1r {v30.2d}, [x1], #8 [1;35mNEON[0;m
813 0x~~~~~~~~~~~~~~~~ 0d40c818 ld1r {v24.2s}, [x0] [1;35mNEON[0;m
[all …]
|
| D | log-all | 1961 0x~~~~~~~~~~~~~~~~ 4d40c002 ld1r {v2.16b}, [x0]
1963 0x~~~~~~~~~~~~~~~~ 4dc2c022 ld1r {v2.16b}, [x1], x2
1966 0x~~~~~~~~~~~~~~~~ 4ddfc036 ld1r {v22.16b}, [x1], #1
1969 0x~~~~~~~~~~~~~~~~ 0d40cc19 ld1r {v25.1d}, [x0]
1971 0x~~~~~~~~~~~~~~~~ 0dc2cc29 ld1r {v9.1d}, [x1], x2
1974 0x~~~~~~~~~~~~~~~~ 0ddfcc37 ld1r {v23.1d}, [x1], #8
1977 0x~~~~~~~~~~~~~~~~ 4d40cc13 ld1r {v19.2d}, [x0]
1979 0x~~~~~~~~~~~~~~~~ 4dc2cc35 ld1r {v21.2d}, [x1], x2
1982 0x~~~~~~~~~~~~~~~~ 4ddfcc3e ld1r {v30.2d}, [x1], #8
1985 0x~~~~~~~~~~~~~~~~ 0d40c818 ld1r {v24.2s}, [x0]
[all …]
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 938 __ ld1r(v2.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
939 __ ld1r(v2.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
940 __ ld1r(v22.V16B(), MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceNEON() local
941 __ ld1r(v25.V1D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
942 __ ld1r(v9.V1D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
943 __ ld1r(v23.V1D(), MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceNEON() local
944 __ ld1r(v19.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
945 __ ld1r(v21.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
946 __ ld1r(v30.V2D(), MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceNEON() local
947 __ ld1r(v24.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
|
| D | test-cpu-features-aarch64.cc | 911 TEST_NEON(ld1r_0, ld1r(v0.V8B(), MemOperand(x1)))
912 TEST_NEON(ld1r_1, ld1r(v0.V16B(), MemOperand(x1)))
913 TEST_NEON(ld1r_2, ld1r(v0.V4H(), MemOperand(x1)))
914 TEST_NEON(ld1r_3, ld1r(v0.V8H(), MemOperand(x1)))
915 TEST_NEON(ld1r_4, ld1r(v0.V2S(), MemOperand(x1)))
916 TEST_NEON(ld1r_5, ld1r(v0.V4S(), MemOperand(x1)))
917 TEST_NEON(ld1r_6, ld1r(v0.V1D(), MemOperand(x1)))
918 TEST_NEON(ld1r_7, ld1r(v0.V2D(), MemOperand(x1)))
919 TEST_NEON(ld1r_8, ld1r(v0.V8B(), MemOperand(x1, 1, PostIndex)))
920 TEST_NEON(ld1r_9, ld1r(v0.V16B(), MemOperand(x1, 1, PostIndex)))
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11855 "ld1\004ld1b\004ld1d\004ld1h\004ld1r\005ld1rb\005ld1rd\005ld1rh\006ld1rq"
14164 …{ 1624 /* ld1r */, AArch64::LD1Rv16b, Convert__TypedVectorList1_1681_0__Reg1_2, Feature_HasNEON, {…
14165 …{ 1624 /* ld1r */, AArch64::LD1Rv1d, Convert__TypedVectorList1_1641_0__Reg1_2, Feature_HasNEON, { …
14166 …{ 1624 /* ld1r */, AArch64::LD1Rv2d, Convert__TypedVectorList1_2641_0__Reg1_2, Feature_HasNEON, { …
14167 …{ 1624 /* ld1r */, AArch64::LD1Rv2s, Convert__TypedVectorList1_2321_0__Reg1_2, Feature_HasNEON, { …
14168 …{ 1624 /* ld1r */, AArch64::LD1Rv4h, Convert__TypedVectorList1_4161_0__Reg1_2, Feature_HasNEON, { …
14169 …{ 1624 /* ld1r */, AArch64::LD1Rv4s, Convert__TypedVectorList1_4321_0__Reg1_2, Feature_HasNEON, { …
14170 …{ 1624 /* ld1r */, AArch64::LD1Rv8b, Convert__TypedVectorList1_881_0__Reg1_2, Feature_HasNEON, { M…
14171 …{ 1624 /* ld1r */, AArch64::LD1Rv8h, Convert__TypedVectorList1_8161_0__Reg1_2, Feature_HasNEON, { …
14172 …{ 1624 /* ld1r */, AArch64::LD1Rv16b, Convert__VecListOne1281_1__Reg1_3, Feature_HasNEON, { MCK__D…
[all …]
|