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Searched refs:ldaxr (Results 1 – 25 of 48) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll179 %val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
193 %val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
202 ; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
207 %val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
216 ; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
219 %val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
225 declare i64 @llvm.aarch64.ldaxr.p0i8(i8*) nounwind
226 declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
227 declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
228 declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
Dfast-isel-cmpxchg.ll6 ; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0]
32 ; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0]
57 ; CHECK-NEXT: ldaxr [[OLD:x[0-9]+]], [x0]
Dcmpxchg-idioms.ll7 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
61 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
97 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x19]
Darm64-atomic.ll7 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
25 ; CHECK-NEXT: ldaxr w[[RESULT:[0-9]+]], [x0]
46 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
96 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
110 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
Dcmpxchg-O0.ll39 ; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]
55 ; CHECK: ldaxr [[OLD:x[0-9]+]], [x0]
Datomic-ops.ll143 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
163 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
223 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
243 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
303 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
383 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
479 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
572 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
742 ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
766 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll179 %val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
193 %val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
202 ; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
207 %val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
216 ; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
219 %val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
225 declare i64 @llvm.aarch64.ldaxr.p0i8(i8*) nounwind
226 declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
227 declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
228 declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
Dcmpxchg-idioms.ll7 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
62 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
Dcmpxchg-O0.ll36 ; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]
51 ; CHECK: ldaxr [[OLD:x[0-9]+]], [x0]
Darm64-atomic.ll7 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
25 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
44 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]
94 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
108 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
Datomic-ops.ll143 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
163 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
223 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
243 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
303 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
383 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
480 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
573 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
743 ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
767 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-memory.s510 ldaxr w2, [x4]
511 ldaxr x2, [x4]
517 ; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
518 ; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
Dbasic-a64-instructions.s2279 ldaxr wzr, [x22]
2280 ldaxr x21, [x23]
/external/llvm/test/MC/AArch64/
Darm64-memory.s510 ldaxr w2, [x4]
511 ldaxr x2, [x4]
517 ; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
518 ; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
Dbasic-a64-instructions.s2296 ldaxr wzr, [x22]
2297 ldaxr x21, [x23]
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1630 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxr, stlxr, Register32); in AssembleArchInstruction()
1633 ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(ldaxr, stlxr, Register); in AssembleArchInstruction()
1657 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTW, Register32); in AssembleArchInstruction()
1660 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTX, Register); in AssembleArchInstruction()
1681 ASSEMBLE_ATOMIC_BINOP(ldaxr, stlxr, inst, Register32); \ in AssembleArchInstruction()
1684 ASSEMBLE_ATOMIC_BINOP(ldaxr, stlxr, inst, Register); \ in AssembleArchInstruction()
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-memory.txt498 # CHECK: ldaxr w2, [x4]
499 # CHECK: ldaxr x2, [x4]
Dbasic-a64-instructions.txt1966 #CHECK: ldaxr w6, [sp]
1967 #CHECK: ldaxr x5, [x6]
1968 #CHECK: ldaxr x5, [x6]
1969 #CHECK: ldaxr x5, [x6]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-memory.txt498 # CHECK: ldaxr w2, [x4]
499 # CHECK: ldaxr x2, [x4]
Dbasic-a64-instructions.txt1950 #CHECK: ldaxr w6, [sp]
1951 #CHECK: ldaxr x5, [x6]
1952 #CHECK: ldaxr x5, [x6]
1953 #CHECK: ldaxr x5, [x6]
/external/vixl/
DREADME.md125 `stlxrh`, `stlxr`, `ldaxrb`, `ldaxrh`, `ldaxr`, `stlxp`, `ldaxp`, `stlrb`,
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs894 0xdf,0xfe,0x5f,0x88 = ldaxr wzr, [x22]
895 0xf5,0xfe,0x5f,0xc8 = ldaxr x21, [x23]
/external/v8/src/arm64/
Dmacro-assembler-arm64.h91 V(Ldaxr, ldaxr) \
Dassembler-arm64.h1641 void ldaxr(const Register& rt, const Register& rn);
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc1924 COMPARE(ldaxr(w21, MemOperand(x22)), "ldaxr w21, [x22]"); in TEST()
1925 COMPARE(ldaxr(w23, MemOperand(sp)), "ldaxr w23, [sp]"); in TEST()
1926 COMPARE(ldaxr(x24, MemOperand(x25)), "ldaxr x24, [x25]"); in TEST()
1927 COMPARE(ldaxr(x26, MemOperand(sp)), "ldaxr x26, [sp]"); in TEST()

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