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Searched refs:ldc2 (Results 1 – 25 of 131) sorted by relevance

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/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips5-wrong-error.s12 …ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
13 …ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
14 …ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed of…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/
Dinvalid-mips2-wrong-error.s9 … ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 … ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips3-wrong-error.s9 … ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 … ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dinvalid-mips4-wrong-error.s11 … ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 … ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips2-wrong-error.s9 …ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signe…
10 …ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signe…
Dinvalid-mips3-wrong-error.s9 …ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
10 …ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
Dinvalid-mips4-wrong-error.s11 …ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
12 …ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit sig…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips5-wrong-error.s12 …ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
13 …ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not…
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid-wrong-error.s31 …ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
32 …ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
33 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid-wrong-error.s41 …ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
42 …ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
43 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll26 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
27 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
49 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll25 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
26 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
48 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
Dinvalid-armv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
Dinvalid-thumbv8.txt154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dintrinsics-coprocessor.ll24 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
25 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
63 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
/external/libunwind_llvm/src/
DUnwindRegistersRestore.S742 ldc2 p1, cr8, [r0], #4 @ wldrw wCGR0, [r0], #4
743 ldc2 p1, cr9, [r0], #4 @ wldrw wCGR1, [r0], #4
744 ldc2 p1, cr10, [r0], #4 @ wldrw wCGR2, [r0], #4
745 ldc2 p1, cr11, [r0], #4 @ wldrw wCGR3, [r0], #4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/
Dinvalid-wrong-error.s17 …ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
18 …ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Ddiagnostics.s309 ldc2 p2, c8, [r1], { 256 }
310 ldc2 p2, c8, [r1], { -1 }
313 @ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 }
316 @ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 }
/external/clang/test/CodeGen/
Dbuiltins-arm.c103 void ldc2(const void *i) { in ldc2() function
/external/llvm/test/MC/Mips/mips2/
Dvalid.s69 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs279 0x01,0x80,0x91,0xfd = ldc2 p0, c8, [r1, #4]
280 0x00,0x71,0x92,0xfd = ldc2 p1, c7, [r2]
281 0x38,0x62,0x13,0xfd = ldc2 p2, c6, [r3, #-224]
282 0x1e,0x53,0x34,0xfd = ldc2 p3, c5, [r4, #-120]!
283 0x04,0x44,0xb5,0xfc = ldc2 p4, c4, [r5], #16
284 0x12,0x35,0x36,0xfc = ldc2 p5, c3, [r6], #-72
315 0x19,0x82,0x91,0xfc = ldc2 p2, c8, [r1], {25}
/external/llvm/test/MC/Mips/
Dmips-fpu-instructions.s177 # CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]
212 ldc2 $11, 12($ra)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips-fpu-instructions.s179 # CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]
214 ldc2 $11, 12($ra)

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