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Searched refs:ldxr (Results 1 – 25 of 47) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll42 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
56 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
65 ; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
70 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
79 ; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
82 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
88 declare i64 @llvm.aarch64.ldxr.p0i8(i8*) nounwind
89 declare i64 @llvm.aarch64.ldxr.p0i16(i16*) nounwind
90 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
91 declare i64 @llvm.aarch64.ldxr.p0i64(i64*) nounwind
Datomic-ops-not-barriers.ll17 ; CHECK: ldxr
Datomic-ops.ll63 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
83 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
323 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
403 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
462 ; ; CHECK: ldxr {{[xw]}}[[OLD]], [x[[ADDR]]]
548 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
646 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
670 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
862 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
940 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
Darm64-atomic.ll64 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
81 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
124 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll42 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
56 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
65 ; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
70 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
79 ; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
82 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
88 declare i64 @llvm.aarch64.ldxr.p0i8(i8*) nounwind
89 declare i64 @llvm.aarch64.ldxr.p0i16(i16*) nounwind
90 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
91 declare i64 @llvm.aarch64.ldxr.p0i64(i64*) nounwind
Datomic-ops-not-barriers.ll17 ; CHECK: ldxr
Datomic-ops.ll63 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
83 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
323 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
403 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
461 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
549 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
647 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
671 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
863 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
941 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
Darm64-atomic.ll62 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
79 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
122 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-memory.s456 ldxr w6, [x1]
457 ldxr x6, [x1]
Dbasic-a64-diagnostics.s1897 ldxr sp, [sp]
Dbasic-a64-instructions.s2251 ldxr w9, [sp]
2252 ldxr x10, [x11]
/external/llvm/test/MC/AArch64/
Darm64-memory.s456 ldxr w6, [x1]
457 ldxr x6, [x1]
Dbasic-a64-diagnostics.s1874 ldxr sp, [sp]
Dbasic-a64-instructions.s2268 ldxr w9, [sp]
2269 ldxr x10, [x11]
/external/vixl/
DREADME.md124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td35 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs882 0xe9,0x7f,0x5f,0x88 = ldxr w9, [sp]
883 0x6a,0x7d,0x5f,0xc8 = ldxr x10, [x11]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-irtranslator.ll1721 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]…
1723 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
1728 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1931 #CHECK: ldxr w22, [sp]
1932 #CHECK: ldxr x11, [x29]
1933 #CHECK: ldxr x11, [x29]
1934 #CHECK: ldxr x11, [x29]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1915 #CHECK: ldxr w22, [sp]
1916 #CHECK: ldxr x11, [x29]
1917 #CHECK: ldxr x11, [x29]
1918 #CHECK: ldxr x11, [x29]
/external/v8/src/s390/
Dconstants-s390.h1509 V(ldxr, LDXR, 0x25) /* type = RR LOAD ROUNDED (extended to long HFP) */ \
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc1892 COMPARE(ldxr(w11, MemOperand(x12)), "ldxr w11, [x12]"); in TEST()
1893 COMPARE(ldxr(w13, MemOperand(sp)), "ldxr w13, [sp]"); in TEST()
1894 COMPARE(ldxr(x14, MemOperand(x15)), "ldxr x14, [x15]"); in TEST()
1895 COMPARE(ldxr(x16, MemOperand(sp)), "ldxr x16, [sp]"); in TEST()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/SystemZ/
Dinsn-good.s8496 #CHECK: ldxr %f0, %f0 # encoding: [0x25,0x00]
8497 #CHECK: ldxr %f0, %f13 # encoding: [0x25,0x0d]
8498 #CHECK: ldxr %f7, %f8 # encoding: [0x25,0x78]
8499 #CHECK: ldxr %f15, %f0 # encoding: [0x25,0xf0]
8500 #CHECK: ldxr %f15, %f13 # encoding: [0x25,0xfd]
8502 ldxr %f0, %f0
8503 ldxr %f0, %f13
8504 ldxr %f7, %f8
8505 ldxr %f15, %f0
8506 ldxr %f15, %f13
/external/vixl/src/aarch64/
Dassembler-aarch64.h1334 void ldxr(const Register& rt, const MemOperand& src);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour169 0x~~~~~~~~~~~~~~~~ 885f7c1b ldxr w27, [x0]
170 0x~~~~~~~~~~~~~~~~ c85f7c1c ldxr x28, [x0]

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