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Searched refs:lhu (Results 1 – 25 of 153) sorted by relevance

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/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dshftopm.ll26 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
27 ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
44 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
64 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
65 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
81 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
100 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
101 ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
118 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
Dlogopm.ll431 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
432 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
451 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
471 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
493 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
494 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
522 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
544 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
545 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
564 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
[all …]
Dloadstoreconv.ll101 ; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
118 ; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
Dretabi.ll34 ; CHECK: lhu $2, 0($[[REG_S_ADDR]])
48 ; CHECK: lhu $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]])
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
Dshftopm.ll26 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
27 ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
44 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
64 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
65 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
81 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
100 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
101 ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
118 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
Dlogopm.ll431 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
432 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
451 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
471 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
493 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
494 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
522 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
544 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
545 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
564 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
[all …]
Dloadstoreconv.ll101 ; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
118 ; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
/external/u-boot/arch/microblaze/cpu/
Dstart.S67 lhu r7, r1, r10
101 lhu r7, r1, r10
114 lhu r7, r1, r10
126 lhu r7, r1, r10
192 in16: lhu r3, r0, r5
262 lhu r7, r1, r10
271 lhu r7, r1, r10
280 lhu r7, r1, r10
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-expansions.s68 lhu $4, 0x8000
70 # CHECK-LE: lhu $4, -32768($4)
72 lhu $4, 0x20004($3)
75 # CHECK-LE: lhu $4, 4($4)
Dmips-memory-instructions.s30 # CHECK: lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94]
40 lhu $4, 4($5)
Dmips64-expansions.s446 lhu $4,0x100010004
451 # CHECK-NEXT: lhu $4, 4($4)
453 lhu $4,0x1800180018004
459 # CHECK-NEXT: lhu $4, -32764($4)
461 lhu $4,0x1800180018004($3)
468 # CHECK-NEXT: lhu $4, -32764($4)
Dmicromips-loadstore-instructions.s15 # CHECK-EL: lhu $4, 8($2) # encoding: [0x82,0x34,0x08,0x00]
74 # CHECK-EB: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
130 lhu $4, 8($2)
/external/llvm/test/CodeGen/Mips/cconv/
Dreturn-struct.ll63 ; O32-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
65 ; O32-DAG: lhu $2, 0([[SP:\$sp]])
68 ; N32-LE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
73 ; N32-BE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
79 ; N64-LE-DAG: lhu [[R2:\$[0-9]+]], 0([[R1]])
84 ; N64-BE-DAG: lhu [[R2:\$[0-9]+]], 0([[R1]])
103 ; O32-BE-DAG: lhu [[R1:\$[0-9]+]], 4([[PTR_LO]])
111 ; O32-LE-DAG: lhu $3, 4([[PTR_LO]])
125 ; N32-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR_LO]])
138 ; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]])
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Dreturn-struct.ll61 ; O32-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
63 ; O32-DAG: lhu $2, 0([[SP:\$sp]])
66 ; N32-LE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
71 ; N32-BE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
78 ; N64-LE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
84 ; N64-BE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)($[[R1]])
103 ; O32-BE-DAG: lhu [[R1:\$[0-9]+]], 4([[PTR_LO]])
111 ; O32-LE-DAG: lhu $3, 4([[PTR_LO]])
125 ; N32-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR_LO]])
138 ; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]])
/external/llvm/test/CodeGen/Mips/
Dunalignedload.ll31 ; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]])
64 ; FIXME: We should be able to do better than this using lhu
66 ; MIPS32R6-EL-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
71 ; FIXME: We should be able to do better than this using lhu
73 ; MIPS32R6-EB-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dunalignedload.ll31 ; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]])
64 ; FIXME: We should be able to do better than this using lhu
66 ; MIPS32R6-EL-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
71 ; FIXME: We should be able to do better than this using lhu
73 ; MIPS32R6-EB-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
/external/llvm/test/MC/Mips/
Dmips-memory-instructions.s30 # CHECK: lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94]
40 lhu $4, 4($5)
Dmicromips-loadstore-instructions.s15 # CHECK-EL: lhu $4, 8($2) # encoding: [0x82,0x34,0x08,0x00]
61 # CHECK-EB: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
104 lhu $4, 8($2)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
Dzext-with-load-is-free.ll5 ; TODO: lbu and lhu should be selected to avoid the unnecessary masking.
50 ; RV32I-NEXT: lhu a2, %lo(shorts)(a0)
54 ; RV32I-NEXT: lhu a0, 2(a0)
Dmem.ll63 define i32 @lhu(i16 *%a) nounwind {
64 ; RV32I-LABEL: lhu:
66 ; RV32I-NEXT: lhu a1, 0(a0)
67 ; RV32I-NEXT: lhu a0, 10(a0)
/external/swiftshader/third_party/LLVM/test/MC/MBlaze/
Dmblaze_memory.s24 # CHECK: lhu
27 lhu r1, r2, r3
/external/capstone/suite/MC/Mips/
Dmicromips-loadstore-instructions.s.cs5 0x82,0x34,0x08,0x00 = lhu $4, 8($2)
Dmicromips-loadstore-instructions-EB.s.cs5 0x34,0x82,0x00,0x08 = lhu $4, 8($2)
Dmips-memory-instructions.s.cs13 0x04,0x00,0xa4,0x94 = lhu $4, 4($5)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips/
Dinvalid.s88 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
92 lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
98 …lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed …
99 …lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed …

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