Searched refs:link_cfg (Results 1 – 3 of 3) sorted by relevance
413 const struct tegra_dp_link_config *link_cfg) in tegra_dc_dp_dump_link_cfg() argument417 link_cfg->max_lane_count); in tegra_dc_dp_dump_link_cfg()419 link_cfg->support_enhanced_framing ? "Y" : "N"); in tegra_dc_dp_dump_link_cfg()421 link_cfg->max_link_bw); in tegra_dc_dp_dump_link_cfg()423 link_cfg->bits_per_pixel); in tegra_dc_dp_dump_link_cfg()425 link_cfg->enhanced_framing ? "Y" : "N"); in tegra_dc_dp_dump_link_cfg()427 link_cfg->scramble_ena ? "Y" : "N"); in tegra_dc_dp_dump_link_cfg()429 link_cfg->link_bw); in tegra_dc_dp_dump_link_cfg()431 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()433 link_cfg->activepolarity); in tegra_dc_dp_dump_link_cfg()[all …]
141 const struct tegra_dp_link_config *link_cfg) in tegra_dc_sor_set_dp_linkctl() argument154 reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT); in tegra_dc_sor_set_dp_linkctl()156 if (link_cfg->enhanced_framing) in tegra_dc_sor_set_dp_linkctl()167 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? in tegra_dc_sor_set_dp_linkctl()274 const struct tegra_dp_link_config *link_cfg) in tegra_dc_sor_set_dp_mode() argument279 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); in tegra_dc_sor_set_dp_mode()281 tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg); in tegra_dc_sor_set_dp_mode()284 reg_val |= link_cfg->watermark; in tegra_dc_sor_set_dp_mode()286 reg_val |= (link_cfg->active_count << in tegra_dc_sor_set_dp_mode()289 reg_val |= (link_cfg->active_frac << in tegra_dc_sor_set_dp_mode()[all …]
879 const struct tegra_dp_link_config *link_cfg);882 u8 training_pattern, const struct tegra_dp_link_config *link_cfg);891 const struct tegra_dp_link_config *link_cfg);893 const struct tegra_dp_link_config *link_cfg);895 const struct tegra_dp_link_config *link_cfg);903 const struct tegra_dp_link_config *link_cfg,