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Searched refs:load5 (Results 1 – 9 of 9) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Ditrans16_dspr2.c25 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_rows_dspr2() local
128 : [load5] "=&r"(load5), [load6] "=&r"(load6), [load7] "=&r"(load7), in idct16_rows_dspr2()
253 : [load5] "=&r"(load5), [load6] "=&r"(load6), [load7] "=&r"(load7), in idct16_rows_dspr2()
304 : [load5] "=&r"(load5), [load6] "=&r"(load6), [step1_10] "=r"(step1_10), in idct16_rows_dspr2()
347 : [load5] "=&r"(load5), [load6] "=&r"(load6) in idct16_rows_dspr2()
381 : [load5] "=&r"(load5), [load6] "=&r"(load6) in idct16_rows_dspr2()
400 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_cols_add_blk_dspr2() local
513 : [load5] "=&r"(load5), [load6] "=&r"(load6), [load7] "=&r"(load7), in idct16_cols_add_blk_dspr2()
639 : [load5] "=&r"(load5), [load6] "=&r"(load6), [load7] "=&r"(load7), in idct16_cols_add_blk_dspr2()
690 : [load5] "=&r"(load5), [load6] "=&r"(load6), [step1_10] "=r"(step1_10), in idct16_cols_add_blk_dspr2()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dhorizontal-store.ll50 …%load5 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 4), align…
51 %cmp4 = icmp sgt i32 %select3, %load5
52 %select4 = select i1 %cmp4, i32 %select3, i32 %load5
97 …%load5 = load i64, i64* getelementptr inbounds ([32 x i64], [32 x i64]* @arr64, i64 0, i64 4), ali…
98 %cmp4 = icmp slt i64 %select3, %load5
99 %select4 = select i1 %cmp4, i64 %select3, i64 %load5
144 …%load5 = load float, float* getelementptr inbounds ([32 x float], [32 x float]* @farr, i64 0, i64 …
145 %cmp4 = fcmp fast ogt float %select3, %load5
146 %select4 = select i1 %cmp4, float %select3, float %load5
191 …%load5 = load double, double* getelementptr inbounds ([32 x double], [32 x double]* @darr, i64 0, …
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/external/llvm/test/CodeGen/Generic/
Dvector-redux.ll32 %wide.load5 = load <4 x i32>, <4 x i32>* %3, align 16
34 %5 = add nsw <4 x i32> %wide.load5, %vec.phi4
41 %wide.load5.1 = load <4 x i32>, <4 x i32>* %9, align 16
43 %11 = add nsw <4 x i32> %wide.load5.1, %5
50 %wide.load5.2 = load <4 x i32>, <4 x i32>* %15, align 16
52 %17 = add nsw <4 x i32> %wide.load5.2, %11
59 %wide.load5.3 = load <4 x i32>, <4 x i32>* %21, align 16
61 %23 = add nsw <4 x i32> %wide.load5.3, %17
68 %wide.load5.4 = load <4 x i32>, <4 x i32>* %27, align 16
70 %29 = add nsw <4 x i32> %wide.load5.4, %23
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Dvector-redux.ll32 %wide.load5 = load <4 x i32>, <4 x i32>* %3, align 16
34 %5 = add nsw <4 x i32> %wide.load5, %vec.phi4
41 %wide.load5.1 = load <4 x i32>, <4 x i32>* %9, align 16
43 %11 = add nsw <4 x i32> %wide.load5.1, %5
50 %wide.load5.2 = load <4 x i32>, <4 x i32>* %15, align 16
52 %17 = add nsw <4 x i32> %wide.load5.2, %11
59 %wide.load5.3 = load <4 x i32>, <4 x i32>* %21, align 16
61 %23 = add nsw <4 x i32> %wide.load5.3, %17
68 %wide.load5.4 = load <4 x i32>, <4 x i32>* %27, align 16
70 %29 = add nsw <4 x i32> %wide.load5.4, %23
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfalkor-hwpf-fix.ll41 %load5 = load i32, i32* %gep5
46 %add3 = add i32 %load5, %load6
Df16-convert.ll63 define double @load5(i16* nocapture readonly %a, i64 %i) nounwind {
64 ; CHECK-LABEL: load5:
/external/llvm/test/CodeGen/AArch64/
Df16-convert.ll63 define double @load5(i16* nocapture readonly %a, i64 %i) nounwind {
64 ; CHECK-LABEL: load5:
/external/llvm/test/Analysis/ValueTracking/
Dmemory-dereferenceable.ll48 %load5 = load i32, i32 addrspace(1)* %nparam
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ValueTracking/
Dmemory-dereferenceable.ll65 %load5 = load i32, i32 addrspace(1)* %nparam