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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dlsr.s10 lsr z0.b, z0.b, #1 label
16 lsr z31.b, z31.b, #8 label
22 lsr z0.h, z0.h, #1 label
28 lsr z31.h, z31.h, #16 label
34 lsr z0.s, z0.s, #1 label
40 lsr z31.s, z31.s, #32 label
46 lsr z0.d, z0.d, #1 label
52 lsr z31.d, z31.d, #64 label
58 lsr z0.b, p0/m, z0.b, #1 label
64 lsr z31.b, p0/m, z31.b, #8 label
[all …]
Dlsr-diagnostics.s3 lsr z30.b, z10.b, #0 label
8 lsr z18.b, z27.b, #9 label
13 lsr z18.b, p0/m, z28.b, #0 label
18 lsr z1.b, p0/m, z9.b, #9 label
23 lsr z26.h, z4.h, #0 label
28 lsr z25.h, z10.h, #17 label
33 lsr z21.h, p0/m, z2.h, #0 label
38 lsr z14.h, p0/m, z30.h, #17 label
43 lsr z17.s, z0.s, #0 label
48 lsr z0.s, z15.s, #33 label
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dremove_lsr.ll4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
36 %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dremove_lsr.ll4 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
5 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
8 ; r17:16 = lsr(r11:10, #32)
11 ; r17:16 = lsr(r11:10, #32)
13 ; This makes the lsr instruction dead and it gets removed subsequently
32 %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
33 %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
34 %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
35 %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
36 %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
[all …]
/external/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
Dlsr-postinc-pos-addrspace.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
10 ; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 2, %entry ]
11 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
12 ; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
13 ; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, -2
17 ; CHECK: inttoptr i32 %lsr.iv.next2 to i8 addrspace(3)*
41 ; CHECK: %lsr.iv1 = phi i64
42 ; CHECK: %lsr.iv = phi i64
43 ; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
44 ; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, -2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/
Dlsr-postinc-pos-addrspace.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
10 ; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ 2, %entry ]
11 ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ %{{[0-9]+}}, %entry ]
12 ; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
13 ; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, -2
17 ; CHECK: inttoptr i32 %lsr.iv.next2 to i8 addrspace(3)*
41 ; CHECK: %lsr.iv1 = phi i64
42 ; CHECK: %lsr.iv = phi i64
43 ; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
44 ; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, -2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Dctlz.ll16 ; CHECK: lsr {{.*}}[[SCRATCH]]
19 ; CHECK: lsr {{.*}}[[RESULT]]
20 ; CHECK: lsr {{.*}}[[RESULT]]
23 ; CHECK: lsr {{.*}}[[SCRATCH]]
24 ; CHECK: lsr {{.*}}[[SCRATCH]]
25 ; CHECK: lsr {{.*}}[[SCRATCH]]
26 ; CHECK: lsr {{.*}}[[SCRATCH]]
30 ; CHECK: lsr {{.*}}[[RESULT]]
35 ; CHECK: lsr {{.*}}[[SCRATCH]]
36 ; CHECK: lsr {{.*}}[[SCRATCH]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
30 %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
[all …]
/external/llvm/test/Analysis/BasicAA/
Dphi-spec-order.ll17 …%lsr.iv4 = phi [16000 x double]* [ %i11, %for.body4 ], [ bitcast (double* getelementptr inbounds (…
19 %lsr.iv1 = phi [16000 x double]* [ %i10, %for.body4 ], [ @X, %for.cond2.preheader ]
21 ; CHECK: NoAlias:{{[ \t]+}}[16000 x double]* %lsr.iv1, [16000 x double]* %lsr.iv4
23 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body4 ], [ 16000, %for.cond2.preheader ]
24 %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>*
25 %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>*
26 %scevgep11 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -2
29 store <4 x double> %add, <4 x double>* %lsr.iv12, align 32
30 %scevgep10 = getelementptr <4 x double>, <4 x double>* %lsr.iv46, i64 -1
33 %scevgep9 = getelementptr <4 x double>, <4 x double>* %lsr.iv12, i64 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dfast-isel-trunc-kill-subreg.ll21 %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
22 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
23 %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
24 %lsr.iv.next4 = add i64 %lsr.iv3, 32
25 %exitcond = icmp eq i32 %lsr.iv.next2, 8
33 %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
34 %lsr.iv.next = add i32 %lsr.iv, 4
35 %tmp272 = icmp slt i32 %lsr.iv.next, 100
/external/llvm/test/CodeGen/X86/
Dfast-isel-trunc-kill-subreg.ll21 %lsr.iv3 = phi i64 [ %lsr.iv.next4, %bb241 ], [ %tmp12, %bb ]
22 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb241 ], [ 0, %bb ]
23 %lsr.iv.next2 = add nuw nsw i32 %lsr.iv1, 1
24 %lsr.iv.next4 = add i64 %lsr.iv3, 32
25 %exitcond = icmp eq i32 %lsr.iv.next2, 8
33 %lsr.iv = phi i32 [ %lsr.iv.next, %bb270 ], [ %tmp18, %.preheader.preheader ]
34 %lsr.iv.next = add i32 %lsr.iv, 4
35 %tmp272 = icmp slt i32 %lsr.iv.next, 100
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
8 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
11 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
14 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
17 ldrt r1, [r0], r2, lsr #3
20 ldrbt r1, [r0], r2, lsr #3
23 strt r1, [r0], r2, lsr #3
26 strbt r1, [r0], r2, lsr #3
30 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
31 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
/external/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
17 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
21 ldrt r1, [r0], r2, lsr #3
25 ldrbt r1, [r0], r2, lsr #3
29 strt r1, [r0], r2, lsr #3
33 strbt r1, [r0], r2, lsr #3
38 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
39 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Darm_addrmode2.s5 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
9 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
13 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
17 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
21 ldrt r1, [r0], r2, lsr #3
25 ldrbt r1, [r0], r2, lsr #3
29 strt r1, [r0], r2, lsr #3
33 strbt r1, [r0], r2, lsr #3
38 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
39 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
[all …]
Darm-shift-encoding.s4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
34 @ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35 @ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AVR/
Dinst-lsr.s6 lsr r31
7 lsr r25
8 lsr r5
9 lsr r0
11 ; CHECK: lsr r31 ; encoding: [0xf6,0x95]
12 ; CHECK: lsr r25 ; encoding: [0x96,0x95]
13 ; CHECK: lsr r5 ; encoding: [0x56,0x94]
14 ; CHECK: lsr r0 ; encoding: [0x06,0x94]
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s54 and w1, w2, w3, lsr #2
55 and x1, x2, x3, lsr #2
65 ; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
66 ; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
76 ands w1, w2, w3, lsr #2
77 ands x1, x2, x3, lsr #2
87 ; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
88 ; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
98 bic w1, w2, w3, lsr #3
99 bic x1, x2, x3, lsr #3
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-logical-encoding.s54 and w1, w2, w3, lsr #2
55 and x1, x2, x3, lsr #2
65 ; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
66 ; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
76 ands w1, w2, w3, lsr #2
77 ands x1, x2, x3, lsr #2
87 ; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
88 ; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
98 bic w1, w2, w3, lsr #3
99 bic x1, x2, x3, lsr #3
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dloop_break.ll53 %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
54 %lsr.iv.next = add i32 %lsr.iv, 1
55 %cmp0 = icmp slt i32 %lsr.iv.next, 0
70 ; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
82 ; OPT-NEXT: %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
97 %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
98 %lsr.iv.next = add i32 %lsr.iv, 1
99 %cmp0 = icmp slt i32 %lsr.iv.next, 0
108 %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
123 ; OPT-NEXT: %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
[all …]
/external/boringssl/ios-arm/crypto/fipsmodule/
Daes-armv4.S258 mov r4,r0,lsr#24 @ write output in endian-neutral
259 mov r5,r0,lsr#16 @ manner...
260 mov r6,r0,lsr#8
263 mov r4,r1,lsr#24
265 mov r5,r1,lsr#16
267 mov r6,r1,lsr#8
270 mov r4,r2,lsr#24
272 mov r5,r2,lsr#16
274 mov r6,r2,lsr#8
277 mov r4,r3,lsr#24
[all …]
Dghash-armv4.S90 eor r4,r8,r4,lsr#4
94 eor r5,r9,r5,lsr#4
96 eor r6,r10,r6,lsr#4
98 eor r7,r11,r7,lsr#4
110 eor r4,r8,r4,lsr#4
112 eor r5,r9,r5,lsr#4
115 eor r6,r10,r6,lsr#4
121 eor r7,r11,r7,lsr#4
128 eor r4,r8,r4,lsr#4
134 eor r5,r9,r5,lsr#4
[all …]
/external/boringssl/linux-arm/crypto/fipsmodule/
Daes-armv4.S257 mov r4,r0,lsr#24 @ write output in endian-neutral
258 mov r5,r0,lsr#16 @ manner...
259 mov r6,r0,lsr#8
262 mov r4,r1,lsr#24
264 mov r5,r1,lsr#16
266 mov r6,r1,lsr#8
269 mov r4,r2,lsr#24
271 mov r5,r2,lsr#16
273 mov r6,r2,lsr#8
276 mov r4,r3,lsr#24
[all …]
/external/u-boot/arch/arm/include/asm/
Dassembler.h24 #define lspull lsr
27 #define get_byte_1 lsr #8
28 #define get_byte_2 lsr #16
29 #define get_byte_3 lsr #24
36 #define lspush lsr
37 #define get_byte_0 lsr #24
38 #define get_byte_1 lsr #16
39 #define get_byte_2 lsr #8
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs17 0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1
18 0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #31
19 0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #32
26 0x38,0x69,0xa7,0xe0 = adc r6, r7, r8, lsr r9
33 0xa5,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #1
34 0xa5,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsr #31
35 0x25,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #32
43 0x37,0x69,0xa6,0xe0 = adc r6, r6, r7, lsr r9
50 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5
51 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5
[all …]

12345678910>>...26