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Searched refs:lwu (Results 1 – 25 of 79) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Drv64i-valid.s7 # CHECK-INST: lwu zero, 4(ra)
9 lwu x0, 4(x1) label
10 # CHECK-INST: lwu sp, 4(gp)
12 lwu x2, +4(x3) label
13 # CHECK-INST: lwu tp, -2048(t0)
15 lwu x4, -2048(x5) label
16 # CHECK-INST: lwu t1, -2048(t2)
18 lwu x6, %lo(2048)(x7) label
19 # CHECK-INST: lwu s0, 2047(s1)
21 lwu x8, 2047(x9) label
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmips64signextendsesf.ll16 ; CHECK-NOT: lwu
30 ; CHECK-NOT: lwu
44 ; CHECK-NOT: lwu
58 ; CHECK-NOT: lwu
72 ; CHECK-NOT: lwu
86 ; CHECK-NOT: lwu
98 ; CHECK-NOT: lwu
110 ; CHECK-NOT: lwu
124 ; CHECK-NOT: lwu
141 ; CHECK-NOT: lwu
[all …]
Dmips64intldst.ll96 ; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]])
99 ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
/external/llvm/test/CodeGen/Mips/
Dmips64signextendsesf.ll16 ; CHECK-NOT: lwu
30 ; CHECK-NOT: lwu
44 ; CHECK-NOT: lwu
58 ; CHECK-NOT: lwu
72 ; CHECK-NOT: lwu
86 ; CHECK-NOT: lwu
98 ; CHECK-NOT: lwu
110 ; CHECK-NOT: lwu
124 ; CHECK-NOT: lwu
141 ; CHECK-NOT: lwu
[all …]
Dmips64intldst.ll96 ; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]])
99 ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid-wrong-error.s11 …lwu $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not …
12 …lwu $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not …
13 …lwu $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not …
/external/llvm/test/MC/Mips/
Dmicromips-loadstore-instructions.s25 # CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0]
71 # CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
114 lwu $2, 8($4)
Dmicromips-invalid.s91 lwu $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-loadstore-instructions.s25 # CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0]
84 # CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
140 lwu $2, 8($4)
Dmicromips-invalid.s91 lwu $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dmips64intldst.ll94 ; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]])
97 ; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
/external/llvm/test/CodeGen/Mips/cconv/
Dreturn-struct.ll117 ; N32-LE-DAG: lwu [[R2:\$[0-9]+]], %lo(struct_3xi16)([[PTR_HI]])
131 ; N64-LE-DAG: lwu [[R2:\$[0-9]+]], 0([[PTR]])
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Dreturn-struct.ll117 ; N32-LE-DAG: lwu [[R2:\$[0-9]+]], %lo(struct_3xi16)([[PTR_HI]])
131 ; N64-LE-DAG: lwu [[R2:\$[0-9]+]], %lo(struct_3xi16)([[R0]])
/external/llvm/test/MC/Mips/mips3/
Dvalid.s139 lwu $s3,-24086($v1)
269 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/indirect-jump-hazard/
Djumptables.ll159 ; MIPS64R2-NEXT: lwu $2, 4($sp)
255 ; MIPS64R6-NEXT: lwu $2, 4($sp)
477 ; PIC-MIPS64R2-NEXT: lwu $3, 4($sp)
541 ; PIC-MIPS64R6-NEXT: lwu $3, 4($sp)
/external/llvm/test/MC/Mips/mips64/
Dvalid.s152 lwu $s3,-24086($v1)
319 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s144 lwu $s3,-24086($v1)
298 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips5/
Dvalid.s145 lwu $s3,-24086($v1)
300 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s168 lwu $s3,-24086($v1)
347 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s168 lwu $s3,-24086($v1)
346 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s169 lwu $s3,-24086($v1)
347 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/
Dvalid.s159 lwu $s3,-24086($v1)
345 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s55 …lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed off…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s54 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td65 class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
284 class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{

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