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Searched refs:m_mask (Results 1 – 11 of 11) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c368 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
370 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
372 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
374 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
376 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
378 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
380 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
382 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
384 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dclock.c437 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
439 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
441 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
443 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
445 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
447 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
449 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
451 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
453 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c417 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
419 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
421 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
423 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
425 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
427 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
429 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
431 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
433 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/external/libhevc/common/x86/
Dihevc_chroma_intra_pred_filters_sse42_intr.c288 __m128i src_temp1, src_temp3, src_temp4, src_temp5, src_temp6, m_mask; in ihevc_intra_pred_chroma_dc_sse42() local
317 m_mask = _mm_loadu_si128((__m128i *)&IHEVCE_SHUFFLEMASKY9[0]); in ihevc_intra_pred_chroma_dc_sse42()
352 src_temp4 = _mm_shuffle_epi8(src_temp4, m_mask); in ihevc_intra_pred_chroma_dc_sse42()
381 src_temp4 = _mm_shuffle_epi8(src_temp4, m_mask); in ihevc_intra_pred_chroma_dc_sse42()
402 src_temp4 = _mm_shuffle_epi8(src_temp4, m_mask); in ihevc_intra_pred_chroma_dc_sse42()
Dihevc_chroma_intra_pred_filters_ssse3_intr.c309 __m128i src_temp1, src_temp3, src_temp4, src_temp5, src_temp6, m_mask; in ihevc_intra_pred_chroma_dc_ssse3() local
338 m_mask = _mm_load_si128((__m128i *)&IHEVCE_SHUFFLEMASKY9[0]); in ihevc_intra_pred_chroma_dc_ssse3()
373 src_temp4 = _mm_shuffle_epi8(src_temp4, m_mask); in ihevc_intra_pred_chroma_dc_ssse3()
404 src_temp4 = _mm_shuffle_epi8(src_temp4, m_mask); in ihevc_intra_pred_chroma_dc_ssse3()
428 src_temp4 = _mm_shuffle_epi8(src_temp4, m_mask); in ihevc_intra_pred_chroma_dc_ssse3()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c577 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
579 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
581 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
583 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
585 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
587 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
589 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
591 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
593 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
595 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c646 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
648 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
650 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
652 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
654 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
656 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
658 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
660 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
662 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
664 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
/external/u-boot/arch/arm/mach-tegra/
Dclock.c102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
599 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()
/external/u-boot/arch/arm/include/asm/arch-tegra/
Dclock.h397 u32 m_mask:10; /* DIVM_MASK */ member
/external/vulkan-headers/include/vulkan/
Dvulkan.hpp242 : m_mask(0) in Flags()
247 : m_mask(static_cast<MaskType>(bit)) in Flags()
252 : m_mask(rhs.m_mask) in Flags()
257 : m_mask(flags) in Flags()
263 m_mask = rhs.m_mask; in operator =()
269 m_mask |= rhs.m_mask; in operator |=()
275 m_mask &= rhs.m_mask; in operator &=()
281 m_mask ^= rhs.m_mask; in operator ^=()
308 return !m_mask; in operator !()
314 result.m_mask ^= FlagTraits<BitType>::allFlags; in operator ~()
[all …]
/external/swiftshader/include/vulkan/
Dvulkan.hpp150 : m_mask(0) in Flags()
155 : m_mask(static_cast<MaskType>(bit)) in Flags()
160 : m_mask(rhs.m_mask) in Flags()
165 : m_mask(flags) in Flags()
171 m_mask = rhs.m_mask; in operator =()
177 m_mask |= rhs.m_mask; in operator |=()
183 m_mask &= rhs.m_mask; in operator &=()
189 m_mask ^= rhs.m_mask; in operator ^=()
216 return !m_mask; in operator !()
222 result.m_mask ^= FlagTraits<BitType>::allFlags; in operator ~()
[all …]