| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | leaFixup64.mir | 170 maxAlignment: 0
205 maxAlignment: 0
240 maxAlignment: 0
274 maxAlignment: 0
309 maxAlignment: 0
344 maxAlignment: 0
379 maxAlignment: 0
415 maxAlignment: 0
451 maxAlignment: 0
486 maxAlignment: 0
[all …]
|
| D | leaFixup32.mir | 97 maxAlignment: 0
132 maxAlignment: 0
167 maxAlignment: 0
202 maxAlignment: 0
238 maxAlignment: 0
274 maxAlignment: 0
308 maxAlignment: 0
344 maxAlignment: 0
379 maxAlignment: 0
414 maxAlignment: 0
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/Generic/ |
| D | frame-info.mir | 36 # CHECK-NEXT: maxAlignment:
49 maxAlignment: 4
66 # CHECK-NEXT: maxAlignment:
82 maxAlignment: 4
|
| /external/llvm/test/CodeGen/MIR/Generic/ |
| D | frame-info.mir | 37 # CHECK-NEXT: maxAlignment:
46 maxAlignment: 4
64 # CHECK-NEXT: maxAlignment:
79 maxAlignment: 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/ |
| D | x86-select-ptrtoint.mir | 43 maxAlignment: 4
72 maxAlignment: 4
100 maxAlignment: 4
128 maxAlignment: 4
|
| D | x86-legalize-ptrtoint.mir | 41 maxAlignment: 4
70 maxAlignment: 4
97 maxAlignment: 4
124 maxAlignment: 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | convert-rr-to-ri-instrs-out-of-range.mir | 237 maxAlignment: 0
287 maxAlignment: 0
343 maxAlignment: 0
406 maxAlignment: 0
465 maxAlignment: 0
523 maxAlignment: 0
585 maxAlignment: 0
643 maxAlignment: 0
702 maxAlignment: 0
760 maxAlignment: 0
[all …]
|
| D | convert-rr-to-ri-instrs.mir | 1031 maxAlignment: 0
1087 maxAlignment: 0
1147 maxAlignment: 0
1208 maxAlignment: 0
1267 maxAlignment: 0
1322 maxAlignment: 0
1372 maxAlignment: 0
1426 maxAlignment: 0
1481 maxAlignment: 0
1535 maxAlignment: 0
[all …]
|
| D | convert-rr-to-ri-instrs-R0-special-handling.mir | 106 maxAlignment: 0
160 maxAlignment: 0
214 maxAlignment: 0
267 maxAlignment: 0
317 maxAlignment: 0
365 maxAlignment: 0
412 maxAlignment: 0
|
| D | rlwinm_rldicl_to_andi.mir | 102 maxAlignment: 0
162 maxAlignment: 0
222 maxAlignment: 0
279 maxAlignment: 0
333 maxAlignment: 0
387 maxAlignment: 0
|
| /external/skia/src/gpu/mtl/ |
| D | GrMtlUniformHandler.mm | 177 uint32_t* maxAlignment,
181 if (alignmentMask > *maxAlignment) {
182 *maxAlignment = alignmentMask;
235 uint32_t* maxAlignment;
239 maxAlignment = &fCurrentGeometryUBOMaxAlignment;
243 maxAlignment = &fCurrentFragmentUBOMaxAlignment;
245 get_ubo_aligned_offset(&uni.fUBOffset, currentOffset, maxAlignment, type, arrayCount);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | optimize-if-exec-masking.mir | 170 maxAlignment: 0
228 maxAlignment: 0
285 maxAlignment: 0
344 maxAlignment: 0
404 maxAlignment: 0
464 maxAlignment: 0
526 maxAlignment: 0
586 maxAlignment: 0
643 maxAlignment: 0
700 maxAlignment: 0
|
| D | shrink-vop3-carry-out.mir | 61 maxAlignment: 0
145 maxAlignment: 0
229 maxAlignment: 0
312 maxAlignment: 0
397 maxAlignment: 0
482 maxAlignment: 0
|
| D | fold-imm-f16-f32.mir | 145 maxAlignment: 0
209 maxAlignment: 0
276 maxAlignment: 0
347 maxAlignment: 0
414 maxAlignment: 0
481 maxAlignment: 0
551 maxAlignment: 0
618 maxAlignment: 0
684 maxAlignment: 0
|
| D | constant-fold-imm-immreg.mir | 35 maxAlignment: 0
120 maxAlignment: 0
201 maxAlignment: 0
306 maxAlignment: 0
401 maxAlignment: 0
509 maxAlignment: 0
609 maxAlignment: 0
718 maxAlignment: 0
|
| D | merge-load-store-physreg.mir | 44 maxAlignment: 0
91 maxAlignment: 0
|
| /external/llvm/test/CodeGen/MIR/Lanai/ |
| D | peephole-compare.mir | 201 maxAlignment: 0
248 maxAlignment: 0
296 maxAlignment: 0
346 maxAlignment: 0
396 maxAlignment: 0
446 maxAlignment: 0
496 maxAlignment: 0
563 maxAlignment: 0
658 maxAlignment: 0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Lanai/ |
| D | peephole-compare.mir | 197 maxAlignment: 0
240 maxAlignment: 0
284 maxAlignment: 0
330 maxAlignment: 0
376 maxAlignment: 0
422 maxAlignment: 0
468 maxAlignment: 0
531 maxAlignment: 0
622 maxAlignment: 0
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | indirect-addressing-undef.mir | 79 maxAlignment: 0
135 maxAlignment: 0
190 maxAlignment: 0
247 maxAlignment: 0
303 maxAlignment: 0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/micromips-sizereduction/ |
| D | micromips-no-lwp-swp.mir | 37 maxAlignment: 4
96 maxAlignment: 4
155 maxAlignment: 4
214 maxAlignment: 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | unaligned-memops-mapping.mir | 40 maxAlignment: 1
86 maxAlignment: 1
|
| /external/deqp-deps/glslang/glslang/MachineIndependent/ |
| D | linkValidate.cpp | 1461 int maxAlignment = std140 ? baseAlignmentVec4Std140 : 0; in getBaseAlignment() local
1468 maxAlignment = std::max(maxAlignment, memberAlignment); in getBaseAlignment()
1476 RoundToPow2(size, maxAlignment); in getBaseAlignment()
1478 return maxAlignment; in getBaseAlignment()
1555 int maxAlignment = 0; in getScalarAlignment() local
1562 maxAlignment = std::max(maxAlignment, memberAlignment); in getScalarAlignment()
1567 return maxAlignment; in getScalarAlignment()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/X86/ |
| D | instructions-debug-location.mir | 56 maxAlignment: 4
77 maxAlignment: 4
|
| /external/llvm/test/CodeGen/MIR/X86/ |
| D | instructions-debug-location.mir | 58 maxAlignment: 4
80 maxAlignment: 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/ |
| D | branch-limits-int-micromipsr6.mir | 161 maxAlignment: 1
248 maxAlignment: 1
335 maxAlignment: 1
422 maxAlignment: 1
509 maxAlignment: 1
596 maxAlignment: 1
683 maxAlignment: 1
770 maxAlignment: 1
857 maxAlignment: 1
944 maxAlignment: 1
[all …]
|