Searched refs:mcInst (Results 1 – 5 of 5) sorted by relevance
| /external/capstone/arch/X86/ |
| D | X86Disassembler.c | 65 static void translateRegister(MCInst *mcInst, Reg reg) in translateRegister() argument
75 MCOperand_CreateReg0(mcInst, llvmRegnum); in translateRegister()
92 static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn) in translateSrcIndex() argument
105 MCOperand_CreateReg0(mcInst, baseRegNo); in translateSrcIndex()
107 MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); in translateSrcIndex()
116 static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn) in translateDstIndex() argument
129 MCOperand_CreateReg0(mcInst, baseRegNo); in translateDstIndex()
140 static void translateImmediate(MCInst *mcInst, uint64_t immediate, in translateImmediate() argument
171 uint32_t Opcode = MCInst_getOpcode(mcInst); in translateImmediate()
221 switch (MCInst_getOpcode(mcInst)) { in translateImmediate()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 152 static void translateRegister(MCInst &mcInst, Reg reg) { in translateRegister() argument
161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
170 static void translateImmediate(MCInst &mcInst, uint64_t immediate, in translateImmediate() argument
198 uint32_t Opcode = mcInst.getOpcode(); in translateImmediate()
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
256 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
265 static bool translateRMRegister(MCInst &mcInst, in translateRMRegister() argument
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
303 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) { in translateRMMemory() argument
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 248 static void translateRegister(MCInst &mcInst, Reg reg) { in translateRegister() argument
257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
314 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { in translateSrcIndex() argument
326 mcInst.addOperand(baseReg); in translateSrcIndex()
330 mcInst.addOperand(segmentReg); in translateSrcIndex()
339 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { in translateDstIndex() argument
351 mcInst.addOperand(baseReg); in translateDstIndex()
361 static void translateImmediate(MCInst &mcInst, uint64_t immediate, in translateImmediate() argument
419 switch (mcInst.getOpcode()) { in translateImmediate()
447 mcInst.setOpcode(NewOpc); in translateImmediate()
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| /external/capstone/ |
| D | MCInst.c | 15 #define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
140 MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) in MCOperand_CreateReg1() argument
142 MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); in MCOperand_CreateReg1()
150 void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) in MCOperand_CreateReg0() argument
152 MCOperand *op = &(mcInst->Operands[mcInst->size]); in MCOperand_CreateReg0()
153 mcInst->size++; in MCOperand_CreateReg0()
159 MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) in MCOperand_CreateImm1() argument
161 MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); in MCOperand_CreateImm1()
169 void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) in MCOperand_CreateImm0() argument
171 MCOperand *op = &(mcInst->Operands[mcInst->size]); in MCOperand_CreateImm0()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 268 static void translateRegister(MCInst &mcInst, Reg reg) { in translateRegister() argument
274 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
331 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { in translateSrcIndex() argument
343 mcInst.addOperand(baseReg); in translateSrcIndex()
347 mcInst.addOperand(segmentReg); in translateSrcIndex()
356 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { in translateDstIndex() argument
368 mcInst.addOperand(baseReg); in translateDstIndex()
378 static void translateImmediate(MCInst &mcInst, uint64_t immediate, in translateImmediate() argument
453 switch (mcInst.getOpcode()) { in translateImmediate()
481 mcInst.setOpcode(NewOpc); in translateImmediate()
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