Searched refs:mckr (Results 1 – 10 of 10) sorted by relevance
57 unsigned freq, mckr; in at91_clock_init() local84 mckr = readl(&pmc->mckr); in at91_clock_init()87 if (mckr & (1 << 12)) in at91_clock_init()90 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()94 freq >>= mckr & AT91_PMC_MCKR_PRES_MASK; in at91_clock_init()96 switch (mckr & AT91_PMC_MCKR_MDIV_MASK) { in at91_clock_init()124 void at91_mck_init(u32 mckr) in at91_mck_init() argument129 tmp = readl(&pmc->mckr); in at91_mck_init()138 tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | in at91_mck_init()143 tmp |= mckr & AT91_PMC_MCKR_H32MXDIV; in at91_mck_init()[all …]
115 unsigned freq, mckr; in at91_clock_init() local155 mckr = readl(&pmc->mckr); in at91_clock_init()159 gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); in at91_clock_init()161 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()166 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4)); in at91_clock_init()168 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()173 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? in at91_clock_init()174 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; in at91_clock_init()175 if (mckr & AT91_PMC_MCKR_MDIV_MASK) in at91_clock_init()185 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == in at91_clock_init()[all …]
107 unsigned freq, mckr; in at91_clock_init() local147 mckr = readl(&pmc->mckr); in at91_clock_init()148 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()151 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()154 (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); in at91_clock_init()
44 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { in lowlevel_clock_init()47 tmp = readl(&pmc->mckr); in lowlevel_clock_init()50 writel(tmp, &pmc->mckr); in lowlevel_clock_init()56 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
26 void at91_mck_init(u32 mckr);27 void at91_mck_init_down(u32 mckr);32 void at91_mck_init(u32 mckr);
65 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; in get_h32mxdiv()
41 u32 mckr; /* 0x30 Master Clock Register */ member
32 if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2) in at91_plladiv_clk_get_rate()55 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2), in at91_plladiv_clk_set_rate()56 &pmc->mckr); in at91_plladiv_clk_set_rate()
25 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) in sama5d4_h32mx_clk_get_rate()
235 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | in misc_init_r()236 AT91SAM9_PMC_MDIV_4, &pmc->mckr); in misc_init_r()