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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/PGOProfile/
Dmemop_size_opt.ll1 ; RUN: opt < %s -pgo-memop-opt -verify-dom-info -pgo-memop-count-threshold=90 -pgo-memop-percent-th…
2 ; RUN: opt < %s -passes=pgo-memop-opt -verify-dom-info -pgo-memop-count-threshold=90 -pgo-memop-per…
3 ; RUN: opt < %s -pgo-memop-opt -verify-dom-info -pgo-memop-count-threshold=90 -pgo-memop-percent-th…
5 ; RUN: opt < %s -passes=pgo-memop-opt -verify-dom-info -pgo-memop-count-threshold=90 -pgo-memop-per…
124 ; YAML-NEXT: Pass: pgo-memop-opt
140 ; YAML-NEXT: Pass: pgo-memop-opt
Dmemop_size_opt_zero.ll1 ; Test to ensure the pgo memop optimization pass doesn't try to scale
3 ; RUN: opt < %s -passes=pgo-memop-opt -verify-dom-info -pgo-memop-count-threshold=1 -S | FileCheck …
4 ; RUN: opt < %s -pgo-memop-opt -verify-dom-info -pgo-memop-count-threshold=1 -S | FileCheck %s --ch…
Dmemop_size_annotation.ll2 ; RUN: opt < %s -pgo-instr-use -memop-max-annotations=9 -pgo-test-profile-file=%t.profdata -S | Fil…
3 ; RUN: opt < %s -passes=pgo-instr-use -memop-max-annotations=9 -pgo-test-profile-file=%t.profdata -…
Dmemop_clone.ll1 ; RUN: opt < %s -pgo-memop-opt -verify-dom-info -S | FileCheck %s
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrFragmentsSIMD.td273 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
278 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
279 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
281 // 128-bit memop pattern fragments
282 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
283 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
284 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
285 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
286 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
287 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
[all …]
DX86InstrSSE.td1723 (memop addr:$src)))]>, VEX;
1730 (memop addr:$src)))]>;
1740 (memop addr:$src)))]>,
1749 (memop addr:$src)))]>,
1772 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1782 (memop addr:$src)))]>,
1811 (memop addr:$src)))]>, VEX;
1818 (memop addr:$src)))]>;
1907 (memop addr:$src)))]>;
1914 (memop addr:$src)))]>;
[all …]
DX86InstrMMX.td375 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
381 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-profdata/
Dmemop-size-prof.proftext1 # RUN: llvm-profdata show -memop-sizes -ic-targets -function=foo %s | FileCheck %s --check-prefixes…
2 # RUN: llvm-profdata show -memop-sizes -ic-targets -counts -text -function=foo %s | FileCheck %s --…
4 # RUN: llvm-profdata show -memop-sizes -ic-targets -function=foo %t.profdata | FileCheck %s --check…
6 # RUN: llvm-profdata show -memop-sizes -ic-targets -function=foo %t.proftext| FileCheck %s --check-…
/external/vixl/test/aarch32/
Dtest-simulator-cond-rd-memop-immediate-8192-a32.cc146 uint32_t memop[2]; member
3349 const MemOperand& memop);
3390 MemOperand memop(rn, sign, offset, addr_mode); in TestHelper() local
3425 Register base_register = memop.GetBaseRegister(); in TestHelper()
3429 __ Ldr(memop_tmp, MemOperand(input_ptr, offsetof(Inputs, memop) + 4)); in TestHelper()
3435 if (!memop.IsPostIndex()) { in TestHelper()
3436 if (memop.IsImmediate()) { in TestHelper()
3437 if (memop.GetSign().IsPlus()) { in TestHelper()
3438 __ Mov(memop_tmp, memop.GetOffsetImmediate()); in TestHelper()
3441 __ Mov(memop_tmp, -memop.GetOffsetImmediate()); in TestHelper()
[all …]
Dtest-simulator-cond-rd-memop-immediate-512-a32.cc146 uint32_t memop[2]; member
3349 const MemOperand& memop);
3390 MemOperand memop(rn, sign, offset, addr_mode); in TestHelper() local
3425 Register base_register = memop.GetBaseRegister(); in TestHelper()
3429 __ Ldr(memop_tmp, MemOperand(input_ptr, offsetof(Inputs, memop) + 4)); in TestHelper()
3435 if (!memop.IsPostIndex()) { in TestHelper()
3436 if (memop.IsImmediate()) { in TestHelper()
3437 if (memop.GetSign().IsPlus()) { in TestHelper()
3438 __ Mov(memop_tmp, memop.GetOffsetImmediate()); in TestHelper()
3441 __ Mov(memop_tmp, -memop.GetOffsetImmediate()); in TestHelper()
[all …]
Dtest-simulator-cond-rd-memop-rs-a32.cc151 uint32_t memop[2]; member
3360 const MemOperand& memop);
3401 MemOperand memop(rn, sign, rm, addr_mode); in TestHelper() local
3438 Register base_register = memop.GetBaseRegister(); in TestHelper()
3442 __ Ldr(memop_tmp, MemOperand(input_ptr, offsetof(Inputs, memop) + 4)); in TestHelper()
3448 if (!memop.IsPostIndex()) { in TestHelper()
3449 if (memop.IsImmediate()) { in TestHelper()
3450 if (memop.GetSign().IsPlus()) { in TestHelper()
3451 __ Mov(memop_tmp, memop.GetOffsetImmediate()); in TestHelper()
3454 __ Mov(memop_tmp, -memop.GetOffsetImmediate()); in TestHelper()
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc149 uint32_t memop[2]; member
3354 const MemOperand& memop);
3397 MemOperand memop(rn, sign, rm, shift, amount, addr_mode); in TestHelper() local
3434 Register base_register = memop.GetBaseRegister(); in TestHelper()
3438 __ Ldr(memop_tmp, MemOperand(input_ptr, offsetof(Inputs, memop) + 4)); in TestHelper()
3444 if (!memop.IsPostIndex()) { in TestHelper()
3445 if (memop.IsImmediate()) { in TestHelper()
3446 if (memop.GetSign().IsPlus()) { in TestHelper()
3447 __ Mov(memop_tmp, memop.GetOffsetImmediate()); in TestHelper()
3450 __ Mov(memop_tmp, -memop.GetOffsetImmediate()); in TestHelper()
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc149 uint32_t memop[2]; member
3354 const MemOperand& memop);
3397 MemOperand memop(rn, sign, rm, shift, amount, addr_mode); in TestHelper() local
3434 Register base_register = memop.GetBaseRegister(); in TestHelper()
3438 __ Ldr(memop_tmp, MemOperand(input_ptr, offsetof(Inputs, memop) + 4)); in TestHelper()
3444 if (!memop.IsPostIndex()) { in TestHelper()
3445 if (memop.IsImmediate()) { in TestHelper()
3446 if (memop.GetSign().IsPlus()) { in TestHelper()
3447 __ Mov(memop_tmp, memop.GetOffsetImmediate()); in TestHelper()
3450 __ Mov(memop_tmp, -memop.GetOffsetImmediate()); in TestHelper()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dtrivialmemaliascheck.ll3 ; The two memory addresses in the load and the memop below are trivially
11 ; In the example below, this allows the load to be packetized with the memop.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrXOP.td14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
44 Operand memop, ComplexPattern mem_cpat,
49 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
56 PatFrag memop, X86FoldableSchedWrite sched> {
62 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP,
67 PatFrag memop, X86FoldableSchedWrite sched> {
73 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L,
DX86InstrFMA.td296 RegisterClass RC, Operand memop,
299 memop, RC, sched>;
301 memop, RC, sched>;
303 memop, RC, sched>;
427 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
437 (ins VR128:$src1, VR128:$src2, memop:$src3),
444 (ins VR128:$src1, memop:$src2, VR128:$src3),
449 // memop:$src2
DX86InstrFragmentsSIMD.td718 def memop : PatFrag<(ops node:$ptr), (vecload node:$ptr), [{
724 // 128-bit memop pattern fragments
726 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
727 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
728 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
DX86InstrMMX.td513 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
519 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
/external/llvm/lib/Target/X86/
DX86InstrXOP.td14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
43 Operand memop, ComplexPattern mem_cpat> {
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
53 PatFrag memop> {
59 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
63 PatFrag memop> {
69 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
DX86InstrFMA.td214 RegisterClass RC, Operand memop> {
216 memop, RC>;
218 memop, RC>;
220 memop, RC>;
298 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
309 (ins VR128:$src1, VR128:$src2, memop:$src3),
315 (ins VR128:$src1, memop:$src2, VR128:$src3),
DX86InstrFragmentsSIMD.td715 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
720 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
721 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
723 // 128-bit memop pattern fragments
725 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
726 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
727 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
729 // These are needed to match a scalar memop that is used in a vector-only
/external/eigen/bench/tensors/
DREADME19 …00 -Wno-ignored-attributes -sycl -intelspirmetadata -emit-llvm -no-serial-memop -sycl-compress-nam…
/external/swiftshader/third_party/llvm-7.0/llvm/docs/CommandGuide/
Dllvm-profdata.rst205 .. option:: -memop-sizes
/external/eigen/cmake/
DFindComputeCpp.cmake141 …_FLAGS ${COMPUTECPP_DEVICE_COMPILER_FLAGS} -sycl-compress-name -no-serial-memop -DEIGEN_NO_ASSERTI…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Passes/
DPassRegistry.def188 FUNCTION_PASS("pgo-memop-opt", PGOMemOPSizeOpt())

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