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Searched refs:mfmsr (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/MC/PowerPC/
Dppc64-encoding-bookIII.s12 # CHECK-BE: mfmsr 4 # encoding: [0x7c,0x80,0x00,0xa6]
13 # CHECK-LE: mfmsr 4 # encoding: [0xa6,0x00,0x80,0x7c]
14 mfmsr %r4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-bookIII.s20 # CHECK-BE: mfmsr 4 # encoding: [0x7c,0x80,0x00,0xa6]
21 # CHECK-LE: mfmsr 4 # encoding: [0xa6,0x00,0x80,0x7c]
22 mfmsr %r4
/external/u-boot/arch/powerpc/cpu/mpc86xx/
Dstart.S197 mfmsr r5
347 mfmsr r3
370 mfmsr r3
476 mfmsr r3
514 mfmsr r28 /* Disable interrupts */
855 mfmsr r7
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-bookIII.s.cs4 0x7c,0x80,0x00,0xa6 = mfmsr 4
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dstart.S100 mfmsr r5
110 mfmsr r3
167 mfmsr r5 /* save msr contents */
450 mfmsr r28 /* Disable interrupts */
1050 mfmsr r3 /* now that the vectors have */
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-bookIII.txt9 # CHECK: mfmsr 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-bookIII.txt15 # CHECK: mfmsr 4
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Drelease.S319 mfmsr r13
Dcpu.c304 msr = mfmsr (); in do_reset()
Dcpu_init.c1020 msr = mfmsr(); in arch_preboot_os()
Dstart.S1315 mfmsr r28 /* Disable interrupts */
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dstart.S291 mfmsr r28 /* Disable interrupts */
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCSchedule.td254 // mfmsr SprMFMSR
/external/u-boot/arch/powerpc/include/asm/
Dprocessor.h1145 #define mfmsr() ({unsigned int rval; \ macro
/external/v8/src/ppc/
Dconstants-ppc.h1619 V(mfmsr, MFMSR, 0x7C0000A6) \
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td3585 "mfmsr $RT", IIC_SprMFMSR, []>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td4025 "mfmsr $RT", IIC_SprMFMSR, []>;