| /external/u-boot/drivers/net/phy/ |
| D | realtek.c | 161 unsigned int mii_reg; in rtl8211x_parse_status() local
163 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); in rtl8211x_parse_status()
165 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { in rtl8211x_parse_status()
171 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { in rtl8211x_parse_status()
182 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211x_parse_status()
188 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK) in rtl8211x_parse_status()
194 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX) in rtl8211x_parse_status()
199 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED); in rtl8211x_parse_status()
218 unsigned int mii_reg; in rtl8211f_parse_status() local
222 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS); in rtl8211f_parse_status()
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| D | natsemi.c | 65 int mii_reg; in dp83865_parse_status() local
67 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
69 switch (mii_reg & MIIM_DP83865_SPD_MASK) { in dp83865_parse_status()
85 if (mii_reg & MIIM_DP83865_DPX_FULL) in dp83865_parse_status()
118 int mii_reg; in dp83848_parse_status() local
120 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
122 if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) { in dp83848_parse_status()
128 if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) { in dp83848_parse_status()
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| D | et1011c.c | 43 int mii_reg; in et1011c_parse_status() local
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
48 if (mii_reg & ET1011C_DUPLEX_STATUS) in et1011c_parse_status()
53 speed = mii_reg & ET1011C_SPEED_MASK; in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
58 mii_reg &= ~ET1011C_TX_FIFO_MASK; in et1011c_parse_status()
60 mii_reg | in et1011c_parse_status()
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| D | davicom.c | 43 int mii_reg; in dm9161_parse_status() local
45 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
47 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) in dm9161_parse_status()
52 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) in dm9161_parse_status()
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| D | smsc.c | 17 int mii_reg; in smsc_parse_status() local
19 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in smsc_parse_status()
21 if (mii_reg & (BMSR_100FULL | BMSR_100HALF)) in smsc_parse_status()
26 if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) in smsc_parse_status()
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| D | lxt.c | 22 int mii_reg; in lxt971_parse_status() local
25 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2); in lxt971_parse_status()
26 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; in lxt971_parse_status()
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| D | phy.c | 224 unsigned int mii_reg; in genphy_update_link() local
230 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
236 if (phydev->link && mii_reg & BMSR_LSTATUS) in genphy_update_link()
240 !(mii_reg & BMSR_ANEGCOMPLETE)) { in genphy_update_link()
245 while (!(mii_reg & BMSR_ANEGCOMPLETE)) { in genphy_update_link()
265 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
271 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
273 if (mii_reg & BMSR_LSTATUS) in genphy_update_link()
293 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_parse_link() local
355 if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP)) in genphy_parse_link()
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| D | marvell.c | 156 unsigned int mii_reg; in m88e1xxx_parse_status() local
158 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
160 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && in m88e1xxx_parse_status()
161 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { in m88e1xxx_parse_status()
165 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { in m88e1xxx_parse_status()
176 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
182 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) in m88e1xxx_parse_status()
188 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) in m88e1xxx_parse_status()
193 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; in m88e1xxx_parse_status()
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| D | mv88e61xx.c | 462 unsigned int mii_reg; in mv88e61xx_parse_status() local
464 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1); in mv88e61xx_parse_status()
466 if ((mii_reg & PHY_REG_STATUS1_LINK) && in mv88e61xx_parse_status()
467 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) { in mv88e61xx_parse_status()
471 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) { in mv88e61xx_parse_status()
482 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in mv88e61xx_parse_status()
488 if (mii_reg & PHY_REG_STATUS1_LINK) in mv88e61xx_parse_status()
494 if (mii_reg & PHY_REG_STATUS1_DUPLEX) in mv88e61xx_parse_status()
499 speed = mii_reg & PHY_REG_STATUS1_SPEED; in mv88e61xx_parse_status()
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| D | vitesse.c | 87 int mii_reg; in vitesse_parse_status() local
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
91 if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX) in vitesse_parse_status()
96 speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED; in vitesse_parse_status()
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| D | broadcom.c | 67 unsigned int mii_reg; in bcm54xx_parse_status() local
69 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); in bcm54xx_parse_status()
71 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> in bcm54xx_parse_status()
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| D | mscc.c | 202 u16 mii_reg; in mscc_parse_status() local
204 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG); in mscc_parse_status()
206 if (mii_reg & MIIM_AUX_CNTRL_STAT_F_DUPLEX) in mscc_parse_status()
211 speed = mii_reg & MIIM_AUX_CNTRL_STAT_SPEED_MASK; in mscc_parse_status()
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| /external/u-boot/scripts/coccinelle/net/ |
| D | mdio_register.cocci | 10 @ mii_reg @
27 identifier mii_reg.readfunc;
49 identifier mii_reg.readfunc;
81 identifier mii_reg.readfunc;
99 identifier mii_reg.readfunc;
110 identifier mii_reg.writefunc;
134 identifier mii_reg.writefunc;
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| /external/u-boot/drivers/net/ |
| D | smc91111.c | 887 word mii_reg; in smc_read_phy_register() local
951 mii_reg = SMC_inw (dev, MII_REG); in smc_read_phy_register()
954 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); in smc_read_phy_register()
959 SMC_outw (dev, mii_reg | bits[i], MII_REG); in smc_read_phy_register()
964 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); in smc_read_phy_register()
971 SMC_outw (dev, mii_reg, MII_REG); in smc_read_phy_register()
1005 word mii_reg; in smc_write_phy_register() local
1072 mii_reg = SMC_inw (dev, MII_REG); in smc_write_phy_register()
1075 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); in smc_write_phy_register()
1080 SMC_outw (dev, mii_reg | bits[i], MII_REG); in smc_write_phy_register()
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| /external/u-boot/drivers/qe/ |
| D | uec_phy.c | 130 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; in uec_write_phy_reg() local
151 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; in uec_write_phy_reg()
169 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; in uec_read_phy_reg() local
189 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; in uec_read_phy_reg()
208 mii_id, mii_reg, (u32) & (ug_regs->miimcfg)); in uec_read_phy_reg()
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