| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | simplestorefp1.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
41 ; mips32: .ent d1
42 ; mips32: lui $[[REG1a:[0-9]+]], 16371
43 ; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
44 ; mips32: lui $[[REG1b:[0-9]+]], 21403
45 ; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
[all …]
|
| D | loadstoreconv.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
72 ; mips32-LABEL: .ent _Z4sc_iv
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
83 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
84 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
110 ; mips32=LABEL: .ent _Z4ss_iv
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
121 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | simplestorefp1.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
41 ; mips32: .ent d1
42 ; mips32: lui $[[REG1a:[0-9]+]], 16371
43 ; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
44 ; mips32: lui $[[REG1b:[0-9]+]], 21403
45 ; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
47 ; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
[all …]
|
| D | loadstoreconv.ll | 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
72 ; mips32-LABEL: .ent _Z4sc_iv
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
83 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
84 ; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
110 ; mips32=LABEL: .ent _Z4ss_iv
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
121 ; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | set-mips-directives.s | 16 .set mips32 define
20 .set mips32 define
23 .set mips32 define
52 # CHECK: .set mips32
56 # CHECK: .set mips32
59 # CHECK: .set mips32
|
| D | set-arch.s | 1 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 | \
15 .set arch=mips32
19 .set arch=mips32
22 .set arch=mips32
54 # CHECK: .set arch=mips32
|
| D | directive-ent.s | 4 # RUN: llvm-mc -mcpu=mips32 -triple mips-unknown-unknown %s | \
6 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -triple mips-unknown-unknown %s | \
10 # RUN: llvm-mc -mcpu=mips32 -mattr=micromips -triple mips-unknown-unknown %s | \
12 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -mattr=micromips \
|
| D | llvm-mc-fixup-endianness.s | 1 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck -check-prefi…
2 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mipsel-unknown-unknown %s | FileCheck -check-pre…
|
| D | elf_eflags_nan2008.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | cprestore-reorder.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -show-encoding | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -filetype=obj -o -| \
7 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+micromips --position-independent -show-encoding |…
10 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | \
|
| D | cprestore-noreorder.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -show-encoding | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -filetype=obj -o -| \
7 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+micromips --position-independent -show-encoding |…
10 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | \
|
| D | elf_eflags_nanlegacy.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | elf_eflags_micromips.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 \
4 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - \
|
| /external/llvm/test/MC/Mips/ |
| D | set-mips-directives.s | 16 .set mips32 define
20 .set mips32 define
23 .set mips32 define
52 # CHECK: .set mips32
56 # CHECK: .set mips32
59 # CHECK: .set mips32
|
| D | set-arch.s | 1 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 | \
15 .set arch=mips32
19 .set arch=mips32
22 .set arch=mips32
54 # CHECK: .set arch=mips32
|
| D | directive-ent.s | 4 # RUN: llvm-mc -mcpu=mips32 -triple mips-unknown-unknown %s | \
6 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -triple mips-unknown-unknown %s | \
10 # RUN: llvm-mc -mcpu=mips32 -mattr=micromips -triple mips-unknown-unknown %s | \
12 # RUN: llvm-mc -filetype=obj -mcpu=mips32 -mattr=micromips \
|
| D | llvm-mc-fixup-endianness.s | 1 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck -check-prefi…
2 # RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mipsel-unknown-unknown %s | FileCheck -check-pre…
|
| D | elf_eflags_nan2008.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| D | cprestore-reorder.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -show-encoding | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -filetype=obj -o -| \
7 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+micromips --position-independent -show-encoding |…
10 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | \
|
| D | cprestore-noreorder.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -show-encoding | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 --position-independent -filetype=obj -o -| \
7 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+micromips --position-independent -show-encoding |…
10 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | \
|
| D | elf_eflags_nanlegacy.s | 1 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \
4 # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \
|
| /external/swiftshader/third_party/subzero/tests_lit/assembler/mips32/ |
| D | encoding_trap.ll | 6 ; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
11 ; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
16 ; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
21 ; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
|
| /external/llvm/test/CodeGen/Mips/ |
| D | abicalls.ll | 1 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o …
2 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - |…
6 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-m…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | abicalls.ll | 1 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o …
2 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - |…
11 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-m…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/indirect-jump-hazard/ |
| D | unsupported-mips32.ll | 1 ; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s 2>&1 | …
3 ; Test that mips32 and indirect jump with hazard barriers is not supported.
|