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Searched refs:mr3 (Results 1 – 18 of 18) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a23.c40 .mr3 = 0,
117 writel(dram_para.mr3, &mctl_phy->mr3); in mctl_init()
201 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); in mctl_init()
Ddram_sun8i_a83t.c137 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
142 writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
Ddram_sun8i_a33.c136 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
Ddram_sun6i.c125 writel(MCTL_MR3, &mctl_phy->mr3); in mctl_channel_init()
Ddram_sun9i.c635 writel(mr[3], &mctl_phy->mr3); in mctl_channel_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a23.h27 u32 mr3; member
187 u32 mr3; /* 0x60 mode register 3 */ member
Ddram_sun8i_a33.h77 u32 mr3; /* 0x3c */ member
Ddram_sun8i_a83t.h77 u32 mr3; /* 0x3c */ member
Ddram_sun9i.h110 u32 mr3; /* 0xa8 mode register 3 */ member
Ddram_sun6i.h176 u32 mr3; /* 0x4c mode register 3 */ member
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr.h140 u32 mr3; member
Dstm32mp1_ddr_regs.h160 u32 mr3; /* 0x4C Mode 3*/ member
Dstm32mp1_ddr.c149 DDRPHY_REG_TIMING(mr3),
/external/u-boot/arch/arm/mach-omap2/omap4/
Dsdram_elpida.c310 .mr3 = -1,
/external/u-boot/arch/arm/mach-omap2/omap5/
Dsdram.c442 .mr3 = 0x1,
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip,rk3288-dmc.txt92 mr0..mr3
/external/u-boot/arch/arm/mach-omap2/
Demif-common.c122 if (mr_regs->mr3 > 0) in do_lpddr2_init()
123 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); in do_lpddr2_init()
/external/u-boot/arch/arm/include/asm/
Demif.h1246 s8 mr3; member