| /external/u-boot/arch/x86/cpu/quark/ |
| D | dram.c | 19 static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params) in prepare_mrc_cache() argument
37 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
42 static int mrc_configure_params(struct mrc_params *mrc_params) in mrc_configure_params() argument
55 mrc_params->boot_mode = prepare_mrc_cache(mrc_params); in mrc_configure_params()
56 if (mrc_params->boot_mode) in mrc_configure_params()
57 mrc_params->boot_mode = BM_COLD; in mrc_configure_params()
59 mrc_params->boot_mode = BM_FAST; in mrc_configure_params()
61 mrc_params->boot_mode = BM_COLD; in mrc_configure_params()
71 mrc_params->ecc_enables = 0; in mrc_configure_params()
75 mrc_params->scrambling_enables = 1; in mrc_configure_params()
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| D | mrc.c | 70 static void mrc_adjust_params(struct mrc_params *mrc_params) in mrc_adjust_params() argument
80 mrc_params->status = MRC_SUCCESS; in mrc_adjust_params()
82 dram_width = mrc_params->dram_width; in mrc_adjust_params()
83 rank_enables = mrc_params->rank_enables; in mrc_adjust_params()
84 channel_width = mrc_params->channel_width; in mrc_adjust_params()
92 mrc_params->board_id = 2; /* select x8 layout */ in mrc_adjust_params()
94 mrc_params->board_id = 0; /* select x16 layout */ in mrc_adjust_params()
97 mrc_params->mem_size = 0; in mrc_adjust_params()
100 dram_params = &mrc_params->params; in mrc_adjust_params()
107 mrc_params->column_bits[0] = in mrc_adjust_params()
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| D | smc.h | 507 void clear_self_refresh(struct mrc_params *mrc_params);
508 void prog_ddr_timing_control(struct mrc_params *mrc_params);
509 void prog_decode_before_jedec(struct mrc_params *mrc_params);
510 void perform_ddr_reset(struct mrc_params *mrc_params);
511 void ddrphy_init(struct mrc_params *mrc_params);
512 void perform_jedec_init(struct mrc_params *mrc_params);
513 void set_ddr_init_complete(struct mrc_params *mrc_params);
514 void restore_timings(struct mrc_params *mrc_params);
515 void default_timings(struct mrc_params *mrc_params);
516 void rcvn_cal(struct mrc_params *mrc_params);
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| D | smc.c | 52 void clear_self_refresh(struct mrc_params *mrc_params) in clear_self_refresh() argument
63 void prog_ddr_timing_control(struct mrc_params *mrc_params) in prog_ddr_timing_control() argument
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
99 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
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| D | mrc_util.h | 107 uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
109 void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
111 uint32_t byte_lane_mask(struct mrc_params *mrc_params);
112 uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
113 uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
116 void print_timings(struct mrc_params *mrc_params);
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| D | hte.c | 86 static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, in hte_basic_data_cmp() argument
141 static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, in hte_rw_data_cmp() argument
207 u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) in hte_mem_init() argument
225 msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1); in hte_mem_init()
297 u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr, in hte_basic_write_read() argument
308 errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode); in hte_basic_write_read()
326 u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params, in hte_write_stress_bit_lanes() argument
348 errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT, in hte_write_stress_bit_lanes()
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| D | hte.h | 36 u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag);
37 u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
39 u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
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| D | mrc_util.c | 1022 uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, in sample_dqs() argument
1029 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in sample_dqs()
1046 hte_mem_op(address, mrc_params->first_run, in sample_dqs()
1048 mrc_params->first_run = 0; in sample_dqs()
1089 void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], in find_rising_edge() argument
1097 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in find_rising_edge()
1106 mrc_params->first_run = 1; in find_rising_edge()
1123 sample_result[sample] = sample_dqs(mrc_params, in find_rising_edge()
1199 temp = sample_dqs(mrc_params, channel, rank, rcvn); in find_rising_edge()
1253 uint32_t byte_lane_mask(struct mrc_params *mrc_params) in byte_lane_mask() argument
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| /external/u-boot/arch/x86/include/asm/arch-quark/ |
| D | mrc.h | 108 struct mrc_params { struct
167 void (*init_fn)(struct mrc_params *mrc_params); argument
184 void mrc_init(struct mrc_params *mrc_params);
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