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Searched refs:mret (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dargs-08.ll13 %mret = call { i64, i64, i64, i64 } @bar1()
14 %ret = extractvalue { i64, i64, i64, i64 } %mret, 3
27 %mret = call { i64, i64, i64, i64, i64 } @bar2()
28 %ret = extractvalue { i64, i64, i64, i64, i64 } %mret, 4
40 %mret = call { double, double, double, double } @bar3()
41 %ret = extractvalue { double, double, double, double } %mret, 3
54 %mret = call { double, double, double, double, double } @bar4()
55 %ret = extractvalue { double, double, double, double, double } %mret, 4
Dvec-args-07.ll14 %mret = call { <2 x double>, <2 x double>,
21 <2 x double>, <2 x double> } %mret, 7
36 %mret = call { <2 x double>, <2 x double>,
45 <2 x double> } %mret, 8
/external/llvm/test/CodeGen/SystemZ/
Dargs-08.ll13 %mret = call { i64, i64, i64, i64 } @bar1()
14 %ret = extractvalue { i64, i64, i64, i64 } %mret, 3
27 %mret = call { i64, i64, i64, i64, i64 } @bar2()
28 %ret = extractvalue { i64, i64, i64, i64, i64 } %mret, 4
40 %mret = call { double, double, double, double } @bar3()
41 %ret = extractvalue { double, double, double, double } %mret, 3
54 %mret = call { double, double, double, double, double } @bar4()
55 %ret = extractvalue { double, double, double, double, double } %mret, 4
Dvec-args-07.ll14 %mret = call { <2 x double>, <2 x double>,
21 <2 x double>, <2 x double> } %mret, 7
36 %mret = call { <2 x double>, <2 x double>,
45 <2 x double> } %mret, 8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Dpriv-valid.s20 # CHECK-INST: mret
22 mret label
Dpriv-invalid.s3 mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction label
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
Dinterrupt-attr-nocall.ll41 ; CHECK-RV32-NEXT: mret
75 ; CHECK-RV32-NEXT: mret
106 ; CHECK-RV32-F-NEXT: mret
141 ; CHECK-RV32-F-NEXT: mret
172 ; CHECK-RV32-FD-NEXT: mret
207 ; CHECK-RV32-FD-NEXT: mret
Dinterrupt-attr.ll17 ; Checking for special return instructions (uret, sret, mret).
36 ; CHECK-NEXT: mret
91 ; CHECK-RV32-NEXT: mret
194 ; CHECK-RV32-F-NEXT: mret
297 ; CHECK-RV32-FD-NEXT: mret
336 ; CHECK-RV64-NEXT: mret
439 ; CHECK-RV64-F-NEXT: mret
542 ; CHECK-RV64-FD-NEXT: mret
592 ; CHECK-RV32-NEXT: mret
698 ; CHECK-RV32-F-NEXT: mret
[all …]
/external/ppp/pppd/include/net/
Dppp-comp.h71 int (*compress) __P((void *state, PACKETPTR *mret,
/external/u-boot/arch/riscv/cpu/ax25/
Dstart.S287 mret
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td432 def MRET : Priv<"mret", 0b0011000> {