| /external/cldr/tools/java/org/unicode/cldr/util/data/ |
| D | iso-639-3-macrolanguages.tab | 220 msa bjn A
221 msa btj A
222 msa bve A
223 msa bvu A
224 msa coa A
225 msa dup A
226 msa hji A
227 msa ind A
228 msa jak A
229 msa jax A
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | ase_warnings.ll | 1 ; Check msa warnings.
2 ; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
4 ; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+msa < %s 2>&1 | \
6 ; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
8 ; RUN: llc -march=mips64 -mattr=+mips64r5 -mattr=+msa < %s 2>&1 | \
61 ; MSA_32: warning: the 'msa' ASE requires MIPS32 revision 5 or greater
62 ; MSA_64: warning: the 'msa' ASE requires MIPS64 revision 5 or greater
63 ; MSA_32_NO_WARNING-NOT: warning: the 'msa' ASE requires MIPS32 revision 5 or greater
64 ; MSA_64_NO_WARNING-NOT: warning: the 'msa' ASE requires MIPS64 revision 5 or greater
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| D | fp-contract.ll | 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -fp-contract=off < %s | FileCheck %s --check-prefixes=CH…
6 ; RUN: llc -march=mips -mattr=+msa,+fp64 -fp-contract=fast < %s | FileCheck %s --check-prefixes=CHE…
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | special.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
5 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
7 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \
9 ; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \
|
| D | 2r_vector_scalar.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
|
| D | llvm-stress-sz1-s742806235.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
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| D | elm_move.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| D | llvm-stress-s2501752154-simplified.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
|
| D | llvm-stress-s449609655-simplified.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/ |
| D | special.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
5 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
7 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \
9 ; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \
|
| D | 2r_vector_scalar.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
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| D | llvm-stress-sz1-s742806235.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
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| D | elm_move.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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| D | llvm-stress-s2501752154-simplified.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
|
| D | llvm-stress-s449609655-simplified.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
|
| /external/libvpx/libvpx/vp8/ |
| D | vp8cx.mk | 108 VP8_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/dct_msa.c
109 VP8_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/encodeopt_msa.c
110 VP8_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/quantize_msa.c
111 VP8_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/temporal_filter_msa.c
117 VP8_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/denoising_msa.c
121 VP8_CX_SRCS_REMOVE-$(HAVE_MSA) += encoder/mips/msa/temporal_filter_msa.c
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| D | vp8_common.mk | 111 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/bilinear_filter_msa.c
112 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/copymem_msa.c
113 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/idct_msa.c
114 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/loopfilter_filters_msa.c
115 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/sixtap_filter_msa.c
116 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp8_macros_msa.h
127 VP8_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/mfqe_msa.c
|
| /external/llvm/test/MC/Mips/ |
| D | mips-reginfo-fp64.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
5 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - …
9 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - …
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | mips-reginfo-fp64.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
5 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - …
9 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - …
|
| /external/libvpx/libvpx/vp9/ |
| D | vp9_common.mk | 67 VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct4x4_msa.c
68 VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct8x8_msa.c
69 VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct16x16_msa.c
78 VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_mfqe_msa.c
|
| D | vp9cx.mk | 139 VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_error_msa.c
140 VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct4x4_msa.c
141 VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct8x8_msa.c
142 VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct16x16_msa.c
143 VP9_CX_SRCS-$(HAVE_MSA) += encoder/mips/msa/vp9_fdct_msa.h
|
| /external/llvm/test/MC/Mips/msa/ |
| D | set-msa-directive.s | 3 # CHECK: .set msa
13 .set msa define
|
| D | abiflags.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/ |
| D | set-msa-directive.s | 3 # CHECK: .set msa
13 .set msa define
|
| D | abiflags.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \
|