| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-mul-div.ll | 333 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
341 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
343 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
345 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
347 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
349 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
351 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
353 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
355 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
363 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
[all …]
|
| D | arm64-fast-isel-rem.ll | 16 ; CHECK: msub w0, [[TMP]], w1, w0
24 ; CHECK: msub x0, [[TMP]], x1, x0
32 ; CHECK: msub w0, [[TMP]], w1, w0
40 ; CHECK: msub x0, [[TMP]], x1, x0
|
| D | aarch64-fix-cortex-a53-835769.ll | 67 ; CHECK-NEXT: msub
70 ; CHECK-NOWORKAROUND-NEXT: msub
82 ; CHECK-NEXT: msub
85 ; CHECK-NOWORKAROUND-NEXT: msub
345 ; CHECK-NEXT: msub
348 ; CHECK-NOWORKAROUND-NEXT: msub
361 ; CHECK-NEXT: msub
364 ; CHECK-NOWORKAROUND-NEXT: msub
444 ; CHECK-NEXT: msub
447 ; CHECK-NOWORKAROUND-NEXT: msub
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-mul-div.ll | 333 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
341 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
343 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
345 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
347 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
349 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
351 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
353 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
355 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
363 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
[all …]
|
| D | arm64-fast-isel-rem.ll | 16 ; CHECK: msub w0, [[TMP]], w1, w0
24 ; CHECK: msub x0, [[TMP]], x1, x0
32 ; CHECK: msub w0, [[TMP]], w1, w0
40 ; CHECK: msub x0, [[TMP]], x1, x0
|
| D | aarch64-fix-cortex-a53-835769.ll | 67 ; CHECK-NEXT: msub
70 ; CHECK-NOWORKAROUND-NEXT: msub
82 ; CHECK-NEXT: msub
85 ; CHECK-NOWORKAROUND-NEXT: msub
345 ; CHECK-NEXT: msub
348 ; CHECK-NOWORKAROUND-NEXT: msub
361 ; CHECK-NEXT: msub
364 ; CHECK-NOWORKAROUND-NEXT: msub
444 ; CHECK-NEXT: msub
447 ; CHECK-NOWORKAROUND-NEXT: msub
[all …]
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-multiply-instructions.s | 14 # CHECK-EL: msub $4, $5 # encoding: [0xa4,0x00,0x3c,0xeb]
21 # CHECK-EB: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
25 msub $4, $5
|
| D | micromips-fpu-instructions.s | 68 # CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11]
69 # CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11]
133 # CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
134 # CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
194 msub.s $f2, $f4, $f6, $f8
195 msub.d $f2, $f4, $f6, $f8
|
| D | mips64-alu-instructions.s | 80 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
105 msub $6,$7
|
| D | mips-alu-instructions.s | 84 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
109 msub $6,$7
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | micromips-multiply-instructions.s | 14 # CHECK-EL: msub $4, $5 # encoding: [0xa4,0x00,0x3c,0xeb]
21 # CHECK-EB: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
25 msub $4, $5
|
| D | mips-alu-instructions.s | 84 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
109 msub $6,$7
|
| D | mips64-alu-instructions.s | 80 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
105 msub $6,$7
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
72 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
86 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
162 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
166 ; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
172 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
239 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
250 ; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
254 ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | fmadd1.ll | 1 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
21 ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
83 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
93 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
97 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
173 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
177 ; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
183 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
250 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
261 ; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| /external/capstone/suite/MC/Mips/ |
| D | mips-dsp-instructions.s.cs | 28 0x71,0x4b,0x18,0x04 = msub $ac3, $10, $11
38 0x71,0x4b,0x00,0x04 = msub $10, $11
|
| D | micromips-multiply-instructions.s.cs | 4 0xa4,0x00,0x3c,0xeb = msub $4, $5
|
| D | micromips-multiply-instructions-EB.s.cs | 4 0x00,0xa4,0xeb,0x3c = msub $4, $5
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips32r2.s | 10 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips32r2.s | 10 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | madd-msub.ll | 35 ; CHECK: msub
57 ; CHECK: msub
|
| /external/llvm/test/MC/Mips/dsp/ |
| D | valid.s | 62 …msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x71,0x…
64 …msub $10, $11 # CHECK: msub $10, $11 # encoding: [0x71,0x…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/dsp/ |
| D | valid.s | 62 …msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x71,0x…
64 …msub $10, $11 # CHECK: msub $10, $11 # encoding: [0x71,0x…
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | 3rf_4rf_q.ll | 117 %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
122 declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
142 %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
147 declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/ |
| D | 3rf_4rf_q.ll | 117 %3 = tail call <8 x i16> @llvm.mips.msub.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
122 declare <8 x i16> @llvm.mips.msub.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
142 %3 = tail call <4 x i32> @llvm.mips.msub.q.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
147 declare <4 x i32> @llvm.mips.msub.q.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
|