| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | mul.ll | 196 ; 32R6: muhu $[[T2:[0-9]+]], $5, $7
219 ; MM32R6: muhu $[[T3:[0-9]+]], $5, $7
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | mul.ll | 193 ; 32R6: muhu $[[T1:[0-9]+]], $5, $7
216 ; MM32R6: muhu $[[T1:[0-9]+]], $5, $7
|
| /external/llvm/test/CodeGen/Mips/ |
| D | madd-msub.ll | 76 ; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
197 ; 32R6-DAG: muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | madd-msub.ll | 76 ; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
210 ; 32R6-DAG: muhu $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}}
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | valid.s | 265 muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 101 muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 126 muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| D | valid-mips32r6-el.txt | 105 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
|
| D | valid-mips32r6.txt | 17 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| D | valid-mips32r6-el.txt | 110 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
|
| D | valid-mips32r6.txt | 19 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 154 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
|
| D | valid-mips64r6.txt | 24 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 160 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
|
| D | valid-mips64r6.txt | 26 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
|
| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| D | valid.txt | 261 0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 95 0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 99 0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 500 muhu(rd_hi, rs, reg); in Mulu()
505 muhu(rd_hi, rs, reg); in Mulu()
552 muhu(rd, rs, rt.rm()); in Mulhu()
564 muhu(rd, rs, scratch); in Mulhu()
|
| D | assembler-mips.h | 838 void muhu(Register rd, Register rs, Register rt);
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 108 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
342 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
|
| D | Mips32r6InstrInfo.td | 539 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 129 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
348 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
|
| D | Mips32r6InstrInfo.td | 593 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
|
| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 500 muhu(rd, rs, rt.rm()); in Mulhu()
512 muhu(rd, rs, scratch); in Mulhu()
|