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Searched refs:mul1 (Results 1 – 25 of 167) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Dsum_squares_msa.c18 v4i32 mul0, mul1; in vpx_sum_squares_2d_i16_msa() local
29 DOTP_SH2_SW(diff0, diff1, diff0, diff1, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
30 mul0 += mul1; in vpx_sum_squares_2d_i16_msa()
38 DOTP_SH2_SW(src0, src1, src0, src1, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
39 DPADD_SH2_SW(src2, src3, src2, src3, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
40 DPADD_SH2_SW(src4, src5, src4, src5, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
41 DPADD_SH2_SW(src6, src7, src6, src7, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
42 mul0 += mul1; in vpx_sum_squares_2d_i16_msa()
50 DOTP_SH2_SW(src0, src1, src0, src1, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
51 DPADD_SH2_SW(src2, src3, src2, src3, mul0, mul1); in vpx_sum_squares_2d_i16_msa()
[all …]
/external/llvm/test/Transforms/StraightLineStrengthReduce/
Dslsr-mul.ll15 %mul1 = mul i32 %b1, %s
16 call void @foo(i32 %mul1)
36 %mul1 = mul i32 %b1, %s
37 call void @foo(i32 %mul1)
57 %mul1 = mul i32 %b1, %s
59 call void @foo(i32 %mul1)
81 %mul1 = mul i32 %a1, %b
86 call void @foo(i32 %mul1)
101 ; mul1 = mul0 + bump; // GVN ensures mul1 and mul2 use the same bump.
102 ; mul2 = mul1 + bump;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/StraightLineStrengthReduce/
Dslsr-mul.ll15 %mul1 = mul i32 %b1, %s
16 call void @foo(i32 %mul1)
36 %mul1 = mul i32 %b1, %s
37 call void @foo(i32 %mul1)
57 %mul1 = mul i32 %b1, %s
59 call void @foo(i32 %mul1)
81 %mul1 = mul i32 %a1, %b
86 call void @foo(i32 %mul1)
101 ; mul1 = mul0 + bump; // GVN ensures mul1 and mul2 use the same bump.
102 ; mul2 = mul1 + bump;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfma-aggr-FMF.ll12 %mul1 = fmul contract float %f1, %f2
14 %add = fadd contract float %mul1, %mul2
15 %second_use_of_mul1 = fdiv float %mul1, %add
30 %mul1 = fmul contract float %f1, %f2
32 %add = fadd contract float %mul1, %mul2
33 %second_use_of_mul1 = fdiv float %mul1, %add
/external/boringssl/src/crypto/fipsmodule/bn/asm/
Dx86-mont.pl146 $mul1="mm5";
165 &movd ($mul1,&DWP(0,$ap)); # ap[0]
168 &pmuludq($mul1,$mul0); # ap[0]*bp[0]
169 &movq ($car0,$mul1);
170 &movq ($acc0,$mul1); # I wish movd worked for
173 &pmuludq($mul1,$_n0q); # *=n0
175 &pmuludq($car1,$mul1); # "t[0]"*np[0]*n0
187 &pmuludq($acc1,$mul1); # np[j]*m1
205 &pmuludq($acc1,$mul1); # np[num-1]*m1
225 &movd ($mul1,&DWP(0,$ap)); # ap[0]
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/external/llvm/test/CodeGen/ARM/
Dshifter_operand.ll85 %mul1 = mul i32 %y, 127534
86 %or = or i32 %mul1, %x
97 %mul1 = mul i32 %y, 255068
98 %or = or i32 %mul1, %x
109 %mul1 = mul i32 %y, 510136
110 %or = or i32 %mul1, %x
121 %mul1 = mul i32 %y, 1020272
122 %or = or i32 %mul1, %x
159 %mul1 = mul i32 %y, 127534
160 %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dshifter_operand.ll85 %mul1 = mul i32 %y, 127534
86 %or = or i32 %mul1, %x
97 %mul1 = mul i32 %y, 255068
98 %or = or i32 %mul1, %x
109 %mul1 = mul i32 %y, 510136
110 %or = or i32 %mul1, %x
121 %mul1 = mul i32 %y, 1020272
122 %or = or i32 %mul1, %x
159 %mul1 = mul i32 %y, 127534
160 %arrayidx = getelementptr inbounds i8, i8* %x, i32 %mul1
[all …]
Dcortex-a57-misched-vfma.ll36 %mul1 = fmul float %f1, %f2
39 %add1 = fadd float %mul1, %mul2
75 %mul1 = fmul <2 x float> %f1, %f2
78 %add1 = fadd <2 x float> %mul1, %mul2
113 %mul1 = fmul float %f1, %f2
116 %sub1 = fsub float %mul1, %mul2
152 %mul1 = fmul <2 x float> %f1, %f2
155 %sub1 = fsub <2 x float> %mul1, %mul2
/external/u-boot/arch/arm/mach-at91/arm920t/
Dclock.c52 unsigned input, mul1; in at91_pll_calc() local
65 mul1 = out_freq / input; in at91_pll_calc()
66 if (mul1 > 2048) in at91_pll_calc()
68 if (mul1 < 2) in at91_pll_calc()
71 diff1 = out_freq - input * mul1; in at91_pll_calc()
77 mul = mul1; in at91_pll_calc()
/external/llvm/test/Transforms/InstCombine/
Dadd2.ll218 %mul1 = mul nsw i16 %x, 8
219 %add2 = add nsw i16 %x, %mul1
227 %mul1 = mul nsw i16 %x, 8
228 %add2 = add nsw i16 %mul1, %x
236 %mul1 = mul i16 %a, 2
238 %add = add nsw i16 %mul1, %mul2
246 %mul1 = mul nsw i16 %a, 2
248 %add = add nsw i16 %mul1, %mul2
256 %mul1 = mul nsw i16 %a, 3
258 %add = add nsw i16 %mul1, %mul2
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/
Dmax-addops-inline.ll5 ; CHECK1: %add2 = add nsw i32 %mul1, %add
8 ; CHECK10: %add2 = add nsw i32 %mul1, %add
14 %mul1 = mul nsw i32 %add, %tr
15 %add2 = add nsw i32 %mul1, %add
/external/llvm/test/Transforms/GVN/
D2011-07-07-MatchIntrinsicExtract.ll34 %mul1 = mul i64 %a, %b
35 ret i64 %mul1
39 ; CHECK-NOT: mul1
70 %mul1 = mul i64 %a, %b
71 ret i64 %mul1
75 ; CHECK-NOT: mul1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GVN/
D2011-07-07-MatchIntrinsicExtract.ll34 %mul1 = mul i64 %a, %b
35 ret i64 %mul1
39 ; CHECK-NOT: mul1
70 %mul1 = mul i64 %a, %b
71 ret i64 %mul1
75 ; CHECK-NOT: mul1
/external/swiftshader/third_party/LLVM/test/Transforms/GVN/
D2011-07-07-MatchIntrinsicExtract.ll34 %mul1 = mul i64 %a, %b
35 ret i64 %mul1
39 ; CHECK-NOT: mul1
70 %mul1 = mul i64 %a, %b
71 ret i64 %mul1
75 ; CHECK-NOT: mul1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/NewGVN/
D2011-07-07-MatchIntrinsicExtract.ll36 %mul1 = mul i64 %a, %b
37 %add2 = add i64 %mul1, %umul.0
42 ; CHECK-NOT: mul1
75 %mul1 = mul i64 %a, %b
76 %add2 = add i64 %mul1, %smul.0
81 ; CHECK-NOT: mul1
/external/u-boot/arch/arm/mach-at91/arm926ejs/
Dclock.c52 unsigned input, mul1; in at91_pll_calc() local
69 mul1 = out_freq / input; in at91_pll_calc()
74 if (mul1 > 2048) in at91_pll_calc()
76 if (mul1 < 2) in at91_pll_calc()
79 diff1 = out_freq - input * mul1; in at91_pll_calc()
85 mul = mul1; in at91_pll_calc()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dadd2.ll232 %mul1 = mul nsw i16 %x, 8
233 %add2 = add nsw i16 %x, %mul1
242 %mul1 = mul nsw i16 %x, 8
243 %add2 = add nsw i16 %mul1, %x
252 %mul1 = mul i16 %a, 2
254 %add = add nsw i16 %mul1, %mul2
263 %mul1 = mul nsw i16 %a, 2
265 %add = add nsw i16 %mul1, %mul2
274 %mul1 = mul nsw i16 %a, 3
276 %add = add nsw i16 %mul1, %mul2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfdot2.ll35 %mul1 = fmul half %src1.el1, %src2.el1
38 %acc2 = fadd half %mul1, %acc1
76 %mul1 = fmul float %csrc1.el1, %csrc2.el1
79 %acc2 = fadd float %mul1, %acc1
115 %mul1 = fmul float %csrc1.el1, %csrc2.el1
118 %acc2 = fadd float %mul1, %acc1
152 %mul1 = fmul float %csrc1.el1, %csrc2.el1
155 %acc2 = fadd float %mul1, %acc1
189 %mul1 = fmul float %csrc2.el1, %csrc2.el2
192 %acc2 = fadd float %mul1, %acc1
[all …]
Dearly-inline.ll7 %mul1 = mul i32 %x, %x
8 %mul2 = mul i32 %mul1, %x
9 %mul3 = mul i32 %mul1, %mul2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
Dmixed-fast-nonfast-fp.ll12 %mul1 = fmul fast float %a, %c
16 %add1 = fadd fast float %mul1, %mul3
33 %mul1 = fmul reassoc float %a, %c
37 %add1 = fadd fast float %mul1, %mul3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Ddag-fmf-cse.ll4 ; If fast-math-flags are propagated correctly, the mul1 expression
16 %mul1 = fmul fast float %a, %b
19 %abx2 = fsub fast float %mul1, %mul2
/external/llvm/test/CodeGen/X86/
Ddag-fmf-cse.ll4 ; If fast-math-flags are propagated correctly, the mul1 expression
16 %mul1 = fmul fast float %a, %b
19 %abx2 = fsub fast float %mul1, %mul2
/external/llvm/test/Transforms/Reassociate/
Dcanonicalize-neg-const.ll14 %mul1 = fmul double -1.234000e-01, %y
15 %add2 = fadd double %mul1, %x
30 %mul1 = fmul double %y, -1.234000e-01
31 %add2 = fadd double %mul1, %x
46 %mul1 = fmul double %y, -1.234000e-01
47 %add2 = fsub double %x, %mul1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/AArch64/
Dprefer-fma.ll27 ; CHECK: %mul1 = fmul fast double %1, %2
28 ; CHECK-NEXT: %sub1 = fsub fast double %mul1, %0
30 %mul1 = fmul fast double %1, %4
31 %sub1 = fsub fast double %mul1, %0
/external/llvm/test/Transforms/SimplifyCFG/AArch64/
Dprefer-fma.ll27 ; CHECK: %mul1 = fmul fast double %1, %2
28 ; CHECK-NEXT: %sub1 = fsub fast double %mul1, %0
30 %mul1 = fmul fast double %1, %4
31 %sub1 = fsub fast double %mul1, %0

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