| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_mul.ll | 15 ; CHECK-NOT: mullw
18 ; CHECK-LE-NOT: mullw
21 ; CHECK-VSX-NOT: mullw
24 ; CHECK-LE-VSX-NOT: mullw
34 ; CHECK-NOT: mullw
37 ; CHECK-LE-NOT: mullw
40 ; CHECK-VSX-NOT: mullw
43 ; CHECK-LE-VSX-NOT: mullw
54 ; CHECK-NOT: mullw
59 ; CHECK-LE-NOT: mullw
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_mul.ll | 15 ; CHECK-NOT: mullw
18 ; CHECK-LE-NOT: mullw
21 ; CHECK-VSX-NOT: mullw
24 ; CHECK-LE-VSX-NOT: mullw
34 ; CHECK-NOT: mullw
37 ; CHECK-LE-NOT: mullw
40 ; CHECK-VSX-NOT: mullw
43 ; CHECK-LE-VSX-NOT: mullw
54 ; CHECK-NOT: mullw
59 ; CHECK-LE-NOT: mullw
[all …]
|
| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding.s.cs | 98 0x7c,0x43,0x21,0xd6 = mullw 2, 3, 4
99 0x7c,0x43,0x21,0xd7 = mullw. 2, 3, 4
|
| /external/u-boot/post/lib_powerpc/ |
| D | asm.S | 317 mullw r0,r3,r4
336 mullw r3,r3,r0
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| D | vec_mul.ll | 1 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep mullw
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding.s | 407 # CHECK-BE: mullw 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd6]
408 # CHECK-LE: mullw 2, 3, 4 # encoding: [0xd6,0x21,0x43,0x7c]
409 mullw 2, 3, 4
410 # CHECK-BE: mullw. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd7]
411 # CHECK-LE: mullw. 2, 3, 4 # encoding: [0xd7,0x21,0x43,0x7c]
412 mullw. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding.s | 448 # CHECK-BE: mullw 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd6]
449 # CHECK-LE: mullw 2, 3, 4 # encoding: [0xd6,0x21,0x43,0x7c]
450 mullw 2, 3, 4
451 # CHECK-BE: mullw. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd7]
452 # CHECK-LE: mullw. 2, 3, 4 # encoding: [0xd7,0x21,0x43,0x7c]
453 mullw. 2, 3, 4
|
| /external/v8/src/compiler/ppc/ |
| D | code-generator-ppc.cc | 1282 __ mullw(i.TempRegister(0), i.InputRegister(0), i.InputRegister(3)); in AssembleArchInstruction() local
1283 __ mullw(i.TempRegister(1), i.InputRegister(2), i.InputRegister(1)); in AssembleArchInstruction() local
1285 __ mullw(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2)); in AssembleArchInstruction() local
1443 __ mullw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), in AssembleArchInstruction() local
1458 __ mullw(kScratchReg, in AssembleArchInstruction() local
1464 __ mullw(i.OutputRegister(0), in AssembleArchInstruction() local
1508 ASSEMBLE_MODULO(divw, mullw); in AssembleArchInstruction()
1524 ASSEMBLE_MODULO(divwu, mullw); in AssembleArchInstruction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64le-encoding.txt | 316 # CHECK: mullw 2, 3, 4
319 # CHECK: mullw. 2, 3, 4
|
| D | ppc64-encoding.txt | 319 # CHECK: mullw 2, 3, 4
322 # CHECK: mullw. 2, 3, 4
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding.txt | 319 # CHECK: mullw 2, 3, 4
322 # CHECK: mullw. 2, 3, 4
|
| D | ppc64le-encoding.txt | 316 # CHECK: mullw 2, 3, 4
319 # CHECK: mullw. 2, 3, 4
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCSchedule.td | 279 // mullw IntMulHW
|
| D | PPCInstrInfo.td | 1184 "mullw $rT, $rA, $rB", IntMulHW,
|
| /external/v8/src/ppc/ |
| D | assembler-ppc.h | 1044 void mullw(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
|
| D | constants-ppc.h | 2024 V(mullw, MULLW, 0x7C0001D6) \
|
| D | assembler-ppc.cc | 884 void Assembler::mullw(Register dst, Register src1, Register src2, OEBit o, in mullw() function in v8::internal::Assembler
|
| /external/u-boot/doc/ |
| D | README.POST | 452 subfc, subfe, subme, subze, mullw, mulhw, mulhwu, divw, divwu,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 873 // and the record form is cracked (i.e. divw, mullw, etc.)
2489 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 988 // and the record form is cracked (i.e. divw, mullw, etc.)
2769 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
|