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Searched refs:mxc_ccm (Results 1 – 25 of 31) sorted by relevance

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/external/u-boot/arch/arm/mach-imx/mx5/
Dclock.c73 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; variable
77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
128 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usb_phy1_clk()
142 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy1_clk()
151 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy2_clk()
[all …]
/external/u-boot/board/engicam/imx6q/
Dimx6q.c50 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
56 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
59 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
68 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
71 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
79 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
143 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
150 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
152 writel(reg, &mxc_ccm->CCGR3); in setup_display()
155 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
[all …]
/external/u-boot/arch/arm/mach-imx/mx6/
Dclock.c1317 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_ipu_clock() local
1319 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1321 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1324 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); in enable_ipu_clock()
1325 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in enable_ipu_clock()
1334 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in disable_ldb_di_clock_sources() local
1338 reg = readl(&mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1344 writel(reg, &mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1347 reg = readl(&mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1349 writel(reg, &mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
[all …]
Dsoc.c300 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in set_ahb_rate() local
304 reg = readl(&mxc_ccm->cbcdr); in set_ahb_rate()
307 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); in set_ahb_rate()
312 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in clear_mmdc_ch_mask() local
314 reg = readl(&mxc_ccm->ccdr); in clear_mmdc_ch_mask()
321 writel(reg, &mxc_ccm->ccdr); in clear_mmdc_ch_mask()
619 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in imx_setup_hdmi() local
625 reg = readl(&mxc_ccm->CCGR2); in imx_setup_hdmi()
628 writel(reg, &mxc_ccm->CCGR2); in imx_setup_hdmi()
630 reg = readl(&mxc_ccm->chsccdr); in imx_setup_hdmi()
[all …]
/external/u-boot/board/engicam/imx6ul/
Dimx6ul.c51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
56 clrbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
68 clrbits_le32(&mxc_ccm->cscmr1, in setup_gpmi_nand()
71 clrsetbits_le32(&mxc_ccm->cscdr1, in setup_gpmi_nand()
78 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
86 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/external/u-boot/board/ge/mx53ppd/
Dmx53ppd_video.c79 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in lcd_enable() local
83 clrsetbits_le32(&mxc_ccm->cscmr2, in lcd_enable()
89 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3)); in lcd_enable()
92 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3)); in lcd_enable()
/external/u-boot/board/aristainetos/
Daristainetos.c232 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
239 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
242 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
251 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
254 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
262 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
Daristainetos-v1.c221 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
226 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
230 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
/external/u-boot/board/barco/platinum/
Dplatinum.c65 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
71 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
80 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
88 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/external/u-boot/board/freescale/mx6sabreauto/
Dmx6sabreauto.c365 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
375 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
510 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
519 reg = readl(&mxc_ccm->CCGR3); in setup_display()
521 writel(reg, &mxc_ccm->CCGR3); in setup_display()
524 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
529 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
531 reg = readl(&mxc_ccm->cscmr2); in setup_display()
533 writel(reg, &mxc_ccm->cscmr2); in setup_display()
535 reg = readl(&mxc_ccm->chsccdr); in setup_display()
[all …]
/external/u-boot/board/kosagi/novena/
Dvideo.c386 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_clock() local
394 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_clock()
397 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_display_clock()
402 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_clock()
405 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_clock()
/external/u-boot/board/phytec/pcm058/
Dpcm058.c292 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
298 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
301 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
310 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
313 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
321 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/external/u-boot/board/freescale/mx6sabresd/
Dmx6sabresd.c490 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
501 reg = readl(&mxc_ccm->CCGR3); in setup_display()
503 writel(reg, &mxc_ccm->CCGR3); in setup_display()
506 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
511 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
513 reg = readl(&mxc_ccm->cscmr2); in setup_display()
515 writel(reg, &mxc_ccm->cscmr2); in setup_display()
517 reg = readl(&mxc_ccm->chsccdr); in setup_display()
522 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/external/u-boot/board/gateworks/gw_ventana/
Dgw_ventana.c101 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
107 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
116 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
432 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
439 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
441 writel(reg, &mxc_ccm->CCGR3); in setup_display()
444 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
449 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
451 reg = readl(&mxc_ccm->cscmr2); in setup_display()
[all …]
/external/u-boot/board/toradex/colibri_imx6/
Dcolibri_imx6.c572 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
579 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
581 writel(reg, &mxc_ccm->CCGR3); in setup_display()
584 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
589 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
591 reg = readl(&mxc_ccm->cscmr2); in setup_display()
593 writel(reg, &mxc_ccm->cscmr2); in setup_display()
595 reg = readl(&mxc_ccm->chsccdr); in setup_display()
598 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/external/u-boot/board/boundary/nitrogen6x/
Dnitrogen6x.c756 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
763 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
765 writel(reg, &mxc_ccm->CCGR3); in setup_display()
768 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
773 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
775 reg = readl(&mxc_ccm->cscmr2); in setup_display()
777 writel(reg, &mxc_ccm->cscmr2); in setup_display()
779 reg = readl(&mxc_ccm->chsccdr); in setup_display()
782 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/external/u-boot/board/barco/titanium/
Dtitanium.c158 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
165 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
174 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
182 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/external/u-boot/board/ge/bx50v3/
Dbx50v3.c457 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_b850v3() local
463 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_b850v3()
468 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_b850v3()
474 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_b850v3()
498 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display_bx50v3() local
511 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_bx50v3()
514 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_bx50v3()
520 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_bx50v3()
/external/u-boot/board/phytec/pfla02/
Dpfla02.c274 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_gpmi_nand() local
280 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
283 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
292 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_nand()
295 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
303 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
/external/u-boot/board/embest/mx6boards/
Dmx6boards.c461 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
469 setbits_le32(&mxc_ccm->CCGR3, in setup_display()
473 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_display()
477 setbits_le32(&mxc_ccm->cscmr2, in setup_display()
480 setbits_le32(&mxc_ccm->chsccdr, in setup_display()
/external/u-boot/board/toradex/apalis_imx6/
Dapalis_imx6.c694 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
701 reg = __raw_readl(&mxc_ccm->CCGR3); in setup_display()
703 writel(reg, &mxc_ccm->CCGR3); in setup_display()
706 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
711 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
713 reg = readl(&mxc_ccm->cscmr2); in setup_display()
715 writel(reg, &mxc_ccm->cscmr2); in setup_display()
717 reg = readl(&mxc_ccm->chsccdr); in setup_display()
720 writel(reg, &mxc_ccm->chsccdr); in setup_display()
/external/u-boot/drivers/video/
Dipu_common.c26 extern struct mxc_ccm_reg *mxc_ccm;
169 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_enable()
171 __raw_writel(reg, &mxc_ccm->ccdr); in clk_ipu_enable()
174 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_enable()
176 __raw_writel(reg, &mxc_ccm->clpcr); in clk_ipu_enable()
194 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_disable()
196 __raw_writel(reg, &mxc_ccm->ccdr); in clk_ipu_disable()
199 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_disable()
201 __raw_writel(reg, &mxc_ccm->clpcr); in clk_ipu_disable()
/external/u-boot/board/advantech/dms-ba16/
Ddms-ba16.c397 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
400 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
405 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display()
411 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display()
/external/u-boot/board/k+p/kp_imx6q_tpc/
Dkp_imx6q_tpc.c262 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in board_init() local
268 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); in board_init()
/external/u-boot/board/congatec/cgtqmx6eval/
Dcgtqmx6eval.c628 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
636 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK | in setup_display()
640 reg = readl(&mxc_ccm->cs2cdr); in setup_display()
645 writel(reg, &mxc_ccm->cs2cdr); in setup_display()
647 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | in setup_display()
650 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()

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