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Searched refs:ninf (Results 1 – 25 of 52) sorted by relevance

123

/external/icu/icu4c/source/test/intltest/
Dtsputil.cpp37 double ninf = -uprv_getInfinity();
103 double ninf = -uprv_getInfinity(); in testMaxMin() local
111 maxMinTest(pinf, ninf, pinf, TRUE); in testMaxMin()
112 maxMinTest(pinf, ninf, ninf, FALSE); in testMaxMin()
121 maxMinTest(ninf, pzero, pzero, TRUE); in testMaxMin()
122 maxMinTest(ninf, pzero, ninf, FALSE); in testMaxMin()
123 maxMinTest(ninf, nzero, nzero, TRUE); in testMaxMin()
124 maxMinTest(ninf, nzero, ninf, FALSE); in testMaxMin()
129 maxMinTest(ninf, nan, nan, TRUE); in testMaxMin()
130 maxMinTest(ninf, nan, nan, FALSE); in testMaxMin()
[all …]
/external/u-boot/post/lib_powerpc/fpu/
Dcompare-fp-1.c33 static float ninf; variable
123 ninf = -__builtin_inf (); in fpu_post_test_math6()
126 iuneq (ninf, pinf, 0); in fpu_post_test_math6()
128 iuneq (pinf, ninf, 0); in fpu_post_test_math6()
137 iltgt (ninf, pinf, 1); in fpu_post_test_math6()
139 iltgt (pinf, ninf, 1); in fpu_post_test_math6()
148 iunlt (NaN, ninf, 1); in fpu_post_test_math6()
150 iunlt (pinf, ninf, 0); in fpu_post_test_math6()
152 iunlt (ninf, ninf, 0); in fpu_post_test_math6()
161 iunle (NaN, ninf, 1); in fpu_post_test_math6()
[all …]
/external/libcxx/test/std/utilities/function.objects/unord.hash/
Dfloating.pass.cpp45 std::size_t ninf = h(-INFINITY); in test() local
51 assert(t0 != ninf); in test()
56 assert(tp1 != ninf); in test()
60 assert(t1 != ninf); in test()
63 assert(tn1 != ninf); in test()
65 assert(pinf != ninf); in test()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dsqrt-fastmath-mir.ll34 ; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %0, %1
36 ; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc VFMADD213SSr %1, killed %3, %4
38 ; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %1, %6
39 ; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr killed %7, killed %5
40 ; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %0, %8
41 ; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc VFMADD213SSr %8, killed %9, %4
42 ; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr %8, %6
43 ; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc VMULSSrr killed %11, killed %10
Dfinite-libcalls.ll21 %r = tail call nnan ninf float @llvm.exp.f32(float %x)
37 %r = tail call nnan ninf double @llvm.exp.f64(double %x)
76 %r = tail call nnan ninf x86_fp80 @llvm.exp.f80(x86_fp80 %x)
92 %r = tail call nnan ninf float @llvm.exp2.f32(float %x)
108 %r = tail call nnan ninf double @llvm.exp2.f64(double %x)
147 %r = tail call nnan ninf x86_fp80 @llvm.exp2.f80(x86_fp80 %x)
163 %r = tail call nnan ninf float @llvm.log.f32(float %x)
179 %r = tail call nnan ninf double @llvm.log.f64(double %x)
218 %r = tail call nnan ninf x86_fp80 @llvm.log.f80(x86_fp80 %x)
234 %r = tail call nnan ninf float @llvm.log2.f32(float %x)
[all …]
Dfmf-propagation.ll11 ; CHECK-NEXT: t8: f32 = fadd ninf t7, t4
15 ; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t4
23 %f4 = fadd ninf float %f3, %y
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfp-classify.ll51 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
52 %and = and i1 %ord, %ninf
65 %ninf = fcmp une float %x.fabs, 0xFFF0000000000000
66 %and = and i1 %ord, %ninf
78 %ninf = fcmp une float %x, 0x7FF0000000000000
79 %and = and i1 %ord, %ninf
92 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
93 %and = and i1 %ord, %ninf
106 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
107 %and = and i1 %ord, %ninf
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dfp-classify.ll51 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
52 %and = and i1 %ord, %ninf
65 %ninf = fcmp une float %x.fabs, 0xFFF0000000000000
66 %and = and i1 %ord, %ninf
78 %ninf = fcmp une float %x, 0x7FF0000000000000
79 %and = and i1 %ord, %ninf
92 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
93 %and = and i1 %ord, %ninf
106 %ninf = fcmp une float %x.fabs, 0x7FF0000000000000
107 %and = and i1 %ord, %ninf
[all …]
/external/llvm/test/Transforms/InstSimplify/
Dfast-math.ll49 ; fadd [nnan ninf] X, (fsub [nnan ninf] 0, X) ==> 0
50 ; where nnan and ninf have to occur at least once somewhere in this
59 %t1 = fsub nnan ninf float 0.0, %a
60 %zero1 = fadd nnan ninf float %t1, %a
63 %zero2 = fadd ninf float %t2, %a
65 %t3 = fsub nnan ninf float 0.0, %a
69 %zero4 = fadd nnan ninf float %t4, %a
89 ; CHECK: [[NO_ZERO1:%.*]] = fsub ninf float %a, %a
98 %no_zero1 = fsub ninf float %a, %a
121 ; CHECK: [[NO_ZERO1:%.*]] = fadd ninf float %a, 0.000000e+00
[all …]
/external/llvm/test/Assembler/
Dfast-math-flags.ll87 ; CHECK: %a = fadd nnan ninf float %x, %y
88 %a = fadd ninf nnan float %x, %y
93 ; CHECK: %b_vec = fsub nnan ninf <3 x float> %vec, %vec
94 %b_vec = fsub ninf nnan <3 x float> %vec, %vec
99 ; CHECK: %d = fdiv nnan ninf float %x, %y
100 %d = fdiv ninf nnan float %x, %y
105 ; CHECK: %e_vec = frem nnan ninf <3 x float> %vec, %vec
106 %e_vec = frem ninf nnan <3 x float> %vec, %vec
121 ; CHECK: %a = fadd nnan ninf float %x, %y
122 %a = fadd ninf nnan float %x, %y
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Assembler/
Dfast-math-flags.ll123 ; CHECK: %a = fadd nnan ninf float %x, %y
124 %a = fadd ninf nnan float %x, %y
129 ; CHECK: %b_vec = fsub nnan ninf <3 x float> %vec, %vec
130 %b_vec = fsub ninf nnan <3 x float> %vec, %vec
135 ; CHECK: %d = fdiv nnan ninf float %x, %y
136 %d = fdiv ninf nnan float %x, %y
141 ; CHECK: %e_vec = frem nnan ninf <3 x float> %vec, %vec
142 %e_vec = frem ninf nnan <3 x float> %vec, %vec
157 ; CHECK: %a = fadd nnan ninf afn float %x, %y
158 %a = fadd ninf nnan afn float %x, %y
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
DX86FsubCmpCombine.ll28 %sub.i = fsub ninf <2 x double> %a, %b
42 %sub.i = fsub ninf <2 x double> %a, %b
56 %sub.i1 = fsub ninf <4 x double> %a, %b
69 %sub.i2 = fsub ninf <8 x double> %a, %b
82 %sub.i3 = fsub ninf <4 x float> %a, %b
95 %sub.i4 = fsub ninf <8 x float> %a, %b
107 %sub.i5 = fsub ninf <16 x float> %a, %b
120 %sub.i = fsub ninf <2 x double> %a, %b
134 %sub.i = fsub ninf <4 x double> %a, %b
148 %sub.i1 = fsub ninf <4 x double> undef, undef
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dfast-math.ll94 ; CHECK-NEXT: [[COULD_BE_NAN:%.*]] = fadd ninf float [[T]], [[X]]
98 %could_be_nan = fadd ninf float %t, %x
104 ; CHECK-NEXT: [[T:%.*]] = fsub nnan ninf float -0.000000e+00, [[X:%.*]]
108 %t = fsub nnan ninf float -0.0, %x
120 %zero = fadd nnan ninf float %x, %sub
131 %zero = fadd nnan ninf <2 x float> %sub, %x
135 ; 'ninf' is not required because 'nnan' allows us to assume
150 ; CHECK-NEXT: [[NO_ZERO1:%.*]] = fsub ninf float [[A:%.*]], [[A]]
159 %no_zero1 = fsub ninf float %a, %a
217 ; CHECK-NEXT: [[NO_ZERO1:%.*]] = fadd ninf float [[A:%.*]], 0.000000e+00
[all …]
Dfp-undef.ll402 %r = fsub ninf double 0x7FF0000000000000, undef
434 %r = fdiv ninf double 0x7FF0000000000000, undef
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/X86/
Dfastmath.mir15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1
16 %2:fr32 = ninf VMULSSrr %1, %1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dfmul-sqrt.ll76 ; CHECK-NEXT: [[TMP3:%.*]] = fmul reassoc nnan ninf double [[TMP2]], [[D:%.*]]
77 ; CHECK-NEXT: [[TMP4:%.*]] = call reassoc nnan ninf double @llvm.sqrt.f64(double [[TMP3]])
86 %mul2 = fmul reassoc nnan ninf double %mul1, %4
Dfdiv.ll142 %div1 = fdiv ninf float %x, %y
258 ; CHECK-NEXT: [[DIV:%.*]] = fdiv ninf <2 x float> [[X:%.*]], <float -3.000000e+00, float 8.00000…
262 %div = fdiv ninf <2 x float> %neg, <float 3.0, float -8.0>
268 ; CHECK-NEXT: [[DIV:%.*]] = fdiv ninf <2 x float> [[X:%.*]], <float -3.000000e+00, float 8.00000…
272 %div = fdiv ninf <2 x float> %neg, <float 3.0, float -8.0>
316 ; CHECK-NEXT: [[D:%.*]] = fdiv reassoc nnan ninf nsz <2 x float> <float 1.000000e+00, float 1.00…
320 %d = fdiv nnan ninf nsz reassoc <2 x float> %x, %m
Dfmul.ll7 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf float [[X:%.*]], -2.000000e+01
11 %mul = fmul ninf float %sub, 2.0e+1
17 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf <2 x float> [[X:%.*]], <float -2.000000e+00, float -3.0000…
21 %mul = fmul ninf <2 x float> %sub, <float 2.0, float 3.0>
27 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf <2 x float> [[X:%.*]], <float -2.000000e+00, float -3.0000…
31 %mul = fmul ninf <2 x float> %sub, <float 2.0, float 3.0>
342 ; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc ninf float [[X]], [[X]]
343 ; CHECK-NEXT: [[MUL2:%.*]] = fmul reassoc ninf float [[TMP1]], [[Y:%.*]]
348 %mul2 = fmul reassoc ninf float %x, %mul1
Dminnum.ll295 ; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf <2 x double> @llvm.maxnum.v2f64(<2 x double> [[X:%.*…
296 ; CHECK-NEXT: [[R:%.*]] = fsub nnan ninf <2 x double> <double -0.000000e+00, double -0.000000e+0…
301 %r = call nnan ninf <2 x double> @llvm.minnum.v2f64(<2 x double> %negx, <2 x double> %negy)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfmf-propagation.ll110 ; FMFDEBUG: fma nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+…
133 ; FMFDEBUG: fma nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+…
219 ; FMFDEBUG: fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
223 ; GLOBALDEBUG: fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
250 ; FMFDEBUG: fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
254 ; GLOBALDEBUG: fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
337 ; FMFDEBUG: fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
341 ; GLOBALDEBUG: fmul nnan ninf nsz arcp contract afn reassoc {{t[0-9]+}}
/external/icu/icu4c/source/test/cintltst/
Dputiltst.c373 double ninf = -uprv_getInfinity();
388 remainderTest(1.0, ninf, 1.0);
394 remainderTest(ninf, nan, nan);
/external/clang/test/CodeGenOpenCL/
Drelaxed-fpmath.cl13 // FINITE: fdiv nnan ninf float
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dpropagate_ir_flags.ll180 %op2 = fadd nnan ninf float %load2, 1.0
206 %op2 = fadd ninf float %load2, 1.0
232 %op2 = fadd fast nnan ninf float %load2, 1.0
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dpropagate_ir_flags.ll180 %op2 = fadd nnan ninf float %load2, 1.0
206 %op2 = fadd ninf float %load2, 1.0
232 %op2 = fadd fast nnan ninf float %load2, 1.0
/external/llvm/utils/vim/syntax/
Dllvm.vim31 syn keyword llvmStatement mul nand ne ninf nnan nsw nsz nuw oeq oge ogt ole

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