| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_draw.c | 97 unsigned *num_patches) in si_emit_derived_tess_state() argument
138 *num_patches = sctx->last_num_patches; in si_emit_derived_tess_state()
175 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4; in si_emit_derived_tess_state()
185 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size + in si_emit_derived_tess_state()
189 *num_patches = MIN2(*num_patches, in si_emit_derived_tess_state()
196 *num_patches = MIN2(*num_patches, 40); in si_emit_derived_tess_state()
203 *num_patches = MIN2(*num_patches, one_wave); in si_emit_derived_tess_state()
217 *num_patches = 1; in si_emit_derived_tess_state()
219 sctx->last_num_patches = *num_patches; in si_emit_derived_tess_state()
221 output_patch0_offset = input_patch_size * *num_patches; in si_emit_derived_tess_state()
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| D | si_shader.c | 963 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices; in get_tcs_tes_buffer_address() local
967 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6); in get_tcs_tes_buffer_address()
969 num_patches, ""); in get_tcs_tes_buffer_address()
982 param_stride = num_patches; in get_tcs_tes_buffer_address()
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| /external/libxaac/decoder/ |
| D | ixheaacd_lpp_tran.c | 577 WORD num_patches = hf_generator->pstr_settings->num_patches; in ixheaacd_filter1_lp() local
582 memset(bw_index, 0, sizeof(WORD32) * num_patches); in ixheaacd_filter1_lp()
679 while (patch < num_patches) { in ixheaacd_filter1_lp()
757 WORD32 num_patches = hf_generator->pstr_settings->num_patches; in ixheaacd_low_pow_hf_generator() local
765 ixheaacd_add16(patch_param[num_patches - 1].dst_start_band, in ixheaacd_low_pow_hf_generator()
766 patch_param[num_patches - 1].num_bands_in_patch); in ixheaacd_low_pow_hf_generator()
821 while (patch < num_patches) { in ixheaacd_low_pow_hf_generator()
876 WORD32 num_patches = hf_generator->pstr_settings->num_patches; in ixheaacd_hf_generator() local
886 ixheaacd_add16(patch_param[num_patches - 1].dst_start_band, in ixheaacd_hf_generator()
887 patch_param[num_patches - 1].num_bands_in_patch); in ixheaacd_hf_generator()
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| D | ixheaacd_esbr_envcal.c | 806 WORD32 num_patches; in ixheaacd_createlimiterbands() local
815 num_patches = 0; in ixheaacd_createlimiterbands()
818 if (x_over_qmf[i] != 0) num_patches++; in ixheaacd_createlimiterbands()
821 if (x_over_qmf[i] != 0) num_patches++; in ixheaacd_createlimiterbands()
823 for (i = 0; i < num_patches; i++) { in ixheaacd_createlimiterbands()
827 num_patches = patch_param->num_patches; in ixheaacd_createlimiterbands()
828 for (i = 0; i < num_patches; i++) { in ixheaacd_createlimiterbands()
843 for (k = 1; k < num_patches; k++) { in ixheaacd_createlimiterbands()
847 gate_mode[i] = ixheaacd_num_bands + num_patches - 1; in ixheaacd_createlimiterbands()
866 for (k = 0; k <= num_patches; k++) { in ixheaacd_createlimiterbands()
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| D | ixheaacd_lpp_tran.h | 51 WORD16 num_patches; member
86 WORD32 num_patches; member
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| D | ixheaacd_sbrdec_lpfuncs.c | 94 const ia_patch_param_struct *p_str_patch_param, WORD16 num_patches, in ixheaacd_derive_lim_band_tbl() argument
121 for (k = 0; k < num_patches; k++) { in ixheaacd_derive_lim_band_tbl()
129 for (k = 1; k < num_patches; k++) { in ixheaacd_derive_lim_band_tbl()
133 temp_nr_lim = nr_lim = (num_low_bnd + num_patches) - 1; in ixheaacd_derive_lim_band_tbl()
159 for (i = 0; i <= num_patches; i++) { in ixheaacd_derive_lim_band_tbl()
407 pstr_transposer_settings->num_patches = patch + 1; in ixheaacd_reset_hf_generator()
411 for (patch = 0; patch < pstr_transposer_settings->num_patches; patch++) { in ixheaacd_reset_hf_generator()
1261 ptr_frame_data->patch_param.num_patches = patch; in ixheaacd_generate_hf()
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| D | ixheaacd_env_calc.h | 50 const ia_patch_param_struct *p_str_patch_param, WORD16 num_patches,
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| D | ixheaacd_sbr_dec.c | 134 WORD32 num_patches = 0; in ixheaacd_hbe_repl_spec() local
138 num_patches++; in ixheaacd_hbe_repl_spec()
142 for (patch = (max_stretch - 1); patch < num_patches; patch++) { in ixheaacd_hbe_repl_spec()
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| D | ixheaacd_sbrdecoder.c | 209 ptr_sbr_dec->str_hf_generator.pstr_settings->num_patches, in ixheaacd_sbr_dec_reset()
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| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| D | TensorPatch.h | 104 Index num_patches = 1;
110 num_patches *= (input_dims[i] - patch_dims[i] + 1);
112 m_dimensions[NumDims-1] = num_patches;
127 num_patches *= (input_dims[i] - patch_dims[i] + 1);
129 m_dimensions[0] = num_patches;
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_pipeline.c | 1385 unsigned num_patches; in calculate_tess_state() local
1411 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4; in calculate_tess_state()
1417 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size)); in calculate_tess_state()
1420 num_patches = MIN2(num_patches, in calculate_tess_state()
1427 num_patches = MIN2(num_patches, 40); in calculate_tess_state()
1432 num_patches = MIN2(num_patches, one_wave); in calculate_tess_state()
1435 output_patch0_offset = input_patch_size * num_patches; in calculate_tess_state()
1438 lds_size = output_patch0_offset + output_patch_size * num_patches; in calculate_tess_state()
1457 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) | in calculate_tess_state()
1458 (num_tcs_output_cp << 9) | num_patches; in calculate_tess_state()
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| D | radv_private.h | 1184 unsigned num_patches; member
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_pipe.h | 788 unsigned *num_patches);
791 unsigned num_patches);
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| D | evergreen_state.c | 4361 …tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches) in evergreen_setup_tess_constants() argument
4379 *num_patches = 1; in evergreen_setup_tess_constants()
4419 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0; in evergreen_setup_tess_constants()
4422 lds_size = output_patch0_offset + output_patch_size * *num_patches; in evergreen_setup_tess_constants()
4436 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor); in evergreen_setup_tess_constants()
4458 unsigned num_patches) in evergreen_get_ls_hs_config() argument
4469 return S_028B58_NUM_PATCHES(num_patches) | in evergreen_get_ls_hs_config()
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| D | r600_state_common.c | 1916 unsigned num_patches, dirty_tex_counter, index_offset = 0; in r600_draw_vbo() local
2063 evergreen_setup_tess_constants(rctx, info, &num_patches); in r600_draw_vbo()
2099 num_patches); in r600_draw_vbo()
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | eigen_spatial_convolutions_test.cc | 1511 const Index num_patches = evaluators[0].impl().dimensions()[3]; in PackRhsHelper() local
1531 Index col_offset = internal::random<Index>(0, num_patches - 10); in PackRhsHelper()
1534 Index cols = std::min(block_cols, num_patches - col_offset); in PackRhsHelper()
1548 "; num_patches=", num_patches, " patch_size=", patch_size, in PackRhsHelper()
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| /external/mesa3d/src/amd/common/ |
| D | ac_nir_to_llvm.c | 2796 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices; in get_tcs_tes_buffer_address() local
2801 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9); in get_tcs_tes_buffer_address()
2803 num_patches, ""); in get_tcs_tes_buffer_address()
2816 param_stride = num_patches; in get_tcs_tes_buffer_address()
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