Searched refs:num_pipes (Results 1 – 12 of 12) sorted by relevance
/external/libevent/test/ |
D | bench.c | 69 static int num_pipes, num_active, num_writes; variable 86 if (widx >= num_pipes) in read_cb() 87 widx -= num_pipes; in read_cb() 103 for (cp = pipes, i = 0; i < num_pipes; i++, cp += 2) { in run_once() 113 space = num_pipes / num_active; in run_once() 150 num_pipes = 100; 152 num_writes = num_pipes; 156 num_pipes = atoi(optarg); 171 rl.rlim_cur = rl.rlim_max = num_pipes * 2 + 50; 178 events = calloc(num_pipes, sizeof(struct event)); [all …]
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D | bench_cascade.c | 81 run_once(int num_pipes) in run_once() argument 87 events = (struct event *)calloc(num_pipes, sizeof(struct event)); in run_once() 88 pipes = (evutil_socket_t *)calloc(num_pipes * 2, sizeof(evutil_socket_t)); in run_once() 95 for (cp = pipes, i = 0; i < num_pipes; i++, cp += 2) { in run_once() 109 for (cp = pipes, i = 0; i < num_pipes; i++, cp += 2) { in run_once() 110 evutil_socket_t fd = i < num_pipes - 1 ? cp[3] : -1; in run_once() 127 for (cp = pipes, i = 0; i < num_pipes; i++, cp += 2) { in run_once() 148 int num_pipes = 100; in main() local 157 num_pipes = atoi(optarg); in main() 166 rl.rlim_cur = rl.rlim_max = num_pipes * 2 + 50; in main() [all …]
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/external/libdrm/radeon/ |
D | radeon_surface.c | 104 uint32_t num_pipes; member 221 surf_man->hw_info.num_pipes = 1; in r6_init_hw_info() 224 surf_man->hw_info.num_pipes = 2; in r6_init_hw_info() 227 surf_man->hw_info.num_pipes = 4; in r6_init_hw_info() 230 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info() 233 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info() 376 yalign = tilew * surf_man->hw_info.num_pipes; in r6_surface_init_2d() 382 MAX2(surf_man->hw_info.num_pipes * in r6_surface_init_2d() 506 surf_man->hw_info.num_pipes = 1; in eg_init_hw_info() 509 surf_man->hw_info.num_pipes = 2; in eg_init_hw_info() [all …]
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/external/mesa3d/src/amd/addrlib/inc/chip/r800/ |
D | si_gb_reg.h | 54 unsigned int num_pipes : 3; member 92 unsigned int num_pipes : 3; member
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/external/mesa3d/src/gallium/drivers/r300/ |
D | r300_query.c | 58 q->num_pipes = r300screen->info.r300_num_z_pipes; in r300_create_query() 60 q->num_pipes = r300screen->info.r300_num_gb_pipes; in r300_create_query()
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D | r300_context.h | 289 unsigned num_pipes; member
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D | r300_emit.c | 767 query->num_results += query->num_pipes; in r300_emit_query_end()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | r600_texture.c | 903 unsigned num_pipes = sscreen->info.num_tile_pipes; in si_texture_get_cmask_info() local 912 switch (num_pipes) { in si_texture_get_cmask_info() 934 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_texture_get_cmask_info() 968 unsigned num_pipes = sscreen->info.num_tile_pipes; in r600_texture_get_htile_size() local 987 if (sscreen->info.chip_class >= CIK && num_pipes < 4) in r600_texture_get_htile_size() 988 num_pipes = 4; in r600_texture_get_htile_size() 990 switch (num_pipes) { in r600_texture_get_htile_size() 1023 base_align = num_pipes * pipe_interleave_bytes; in r600_texture_get_htile_size()
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/external/mesa3d/src/gallium/drivers/r600/ |
D | r600_texture.c | 658 unsigned num_pipes = rscreen->info.num_tile_pipes; in r600_texture_get_cmask_info() local 661 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes; in r600_texture_get_cmask_info() 670 unsigned base_align = num_pipes * pipe_interleave_bytes; in r600_texture_get_cmask_info() 737 unsigned num_pipes = rscreen->info.num_tile_pipes; in r600_texture_get_htile_size() local 751 switch (num_pipes) { in r600_texture_get_htile_size() 784 base_align = num_pipes * pipe_interleave_bytes; in r600_texture_get_htile_size()
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D | evergreen_compute.c | 580 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes; in evergreen_emit_dispatch() local 581 unsigned wave_divisor = (16 * num_pipes); in evergreen_emit_dispatch() 605 num_pipes, num_waves, lds_size); in evergreen_emit_dispatch()
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D | evergreen_state.c | 4376 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes; in evergreen_setup_tess_constants() local 4377 unsigned wave_divisor = (16 * num_pipes); in evergreen_setup_tess_constants()
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/external/mesa3d/src/amd/vulkan/ |
D | radv_image.c | 728 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes; in radv_image_get_cmask_info() local 737 switch (num_pipes) { in radv_image_get_cmask_info() 759 unsigned base_align = num_pipes * pipe_interleave_bytes; in radv_image_get_cmask_info()
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