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/external/llvm/test/CodeGen/NVPTX/
Dfma-disable.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
4 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
Drsqrt.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=1 -nvptx-prec-sqrtf32=0 | FileCheck %s
Ddiv-ri.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=0 | FileCheck %s
Dcallchain.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx"
Dconstant-vectors.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-nvidia-cuda"
Dvector-call.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-cuda"
Dsurf-write-cuda.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
4 target triple = "nvptx-unknown-cuda"
Dvec8.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-cuda"
Dload-sext-i1.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Di1-global.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dnvcl-param-align.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Dsurf-write.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Di1-param.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dtex-read-cuda.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
5 target triple = "nvptx-unknown-cuda"
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dfma-disable.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
4 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
Ddiv-ri.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=0 | FileCheck %s
Dcallchain.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx"
Dconstant-vectors.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-nvidia-cuda"
Dsurf-write-cuda.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
2 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
4 target triple = "nvptx-unknown-cuda"
Dload-sext-i1.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Di1-global.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dnvcl-param-align.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
Di1-param.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
4 target triple = "nvptx-nvidia-cuda"
Dsurf-write.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
3 target triple = "nvptx-unknown-nvcl"
/external/clang/test/Misc/
Dnvptx.languageOptsOpenCL.cl1 // REQUIRES: nvptx-registered-target
2 // RUN: %clang_cc1 -x cl -cl-std=CL %s -verify -triple nvptx-unknown-unknown
3 // RUN: %clang_cc1 -x cl -cl-std=CL1.1 %s -verify -triple nvptx-unknown-unknown
4 // RUN: %clang_cc1 -x cl -cl-std=CL1.2 %s -verify -triple nvptx-unknown-unknown
5 // RUN: %clang_cc1 -x cl -cl-std=CL2.0 %s -verify -triple nvptx-unknown-unknown
6 // RUN: %clang_cc1 -x cl -cl-std=CL %s -verify -triple nvptx-unknown-unknown -Wpedantic-core-featur…
7 // RUN: %clang_cc1 -x cl -cl-std=CL1.1 %s -verify -triple nvptx-unknown-unknown -Wpedantic-core-fea…
8 // RUN: %clang_cc1 -x cl -cl-std=CL1.2 %s -verify -triple nvptx-unknown-unknown -Wpedantic-core-fea…
9 // RUN: %clang_cc1 -x cl -cl-std=CL2.0 %s -verify -triple nvptx-unknown-unknown -Wpedantic-core-fea…
114 // Core feature in CL 2.0, but not supported on nvptx

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