offset0 (reference) in projects: external

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:offset0 (Results 1 – 25 of 85) sorted by relevance

12 3 4

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D	load-local-i16.ll	100 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}} 350 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 378 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 416 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3 417 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5 418 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7 447 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 448 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5 450 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7 451 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:14 off… [all …]
D	ds_read2_offset_order.ll	`6 ; offset0 is larger than offset1 10 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3 12 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12`
D	load-local-i32.ll	67 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 80 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7{{$}} 81 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5{{$}} 82 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}} 84 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offs… 85 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offs… 86 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offs…
D	dagcombine-reassociate-bug.ll	`16 %offset0 = add i64 %offset, 1027 17 %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0`
D	ds_read2_superreg.ll	40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset… 115 ; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} 132 ; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} 133 ; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}} 134 ; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}} 175 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 …
/external/llvm/test/MC/AMDGPU/
D	ds-err.s	`10 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 18 ds_write2_b32 v2, v4, v6 offset0:1000000000`
D	ds.s	`17 ds_write_src2_b32 v2 offset0:4 offset1:8 21 ds_write_src2_b64 v2 offset0:4 offset1:8 25 ds_write2_b32 v2, v4, v6 offset0:4 29 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 37 ds_read2_b32 v[8:9], v2 offset0:4 41 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8`
/external/v8/src/arm64/
D	deoptimizer-arm64.cc	45 int offset0 = reg0.code() * reg_size; in CopyRegListToFrame() local 49 if (offset1 == offset0 + reg_size) { in CopyRegListToFrame() 50 masm->Stp(temp0, temp1, MemOperand(dst, offset0)); in CopyRegListToFrame() 52 masm->Str(temp0, MemOperand(dst, offset0)); in CopyRegListToFrame() 76 int offset0 = reg0.code() * reg_size; in RestoreRegList() local 80 if (offset1 == offset0 + reg_size) { in RestoreRegList() 81 masm->Ldp(reg0, reg1, MemOperand(src, offset0)); in RestoreRegList() 83 masm->Ldr(reg0, MemOperand(src, offset0)); in RestoreRegList()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
D	ds.s	`38 ds_write2_b32 v2, v4, v6 offset0:4 42 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 50 ds_read2_b32 v[8:9], v2 offset0:4 54 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 250 ds_wrxchg2_rtn_b32 v[0:1], v0, v0, v0 offset0:127 offset1:255 258 ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255 459 ds_wrxchg2_rtn_b64 v[0:3], v0, v[1:2], v[0:1] offset0:127 offset1:255 467 ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255`
D	ds-err.s	`10 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 18 ds_write2_b32 v2, v4, v6 offset0:1000000000`
/external/mesa3d/src/egl/wayland/wayland-drm/
D	wayland-drm.c	`63 int32_t offset0, int32_t stride0, in create_buffer() argument 80 buffer->offset[0] = offset0; in create_buffer() 137 int32_t offset0, int32_t stride0, in drm_create_planar_buffer() argument 158 offset0, stride0, offset1, stride1, offset2, stride2); in drm_create_planar_buffer() 166 int32_t offset0, int32_t stride0, in drm_create_prime_buffer() argument 171 offset0, stride0, offset1, stride1, offset2, stride2); in drm_create_prime_buffer()`
/external/llvm/test/CodeGen/AMDGPU/
D	load-local-i16.ll	54 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} 68 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}} 69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} 242 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}} 259 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:1{{$}} 270 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3 271 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5 272 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7 281 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}} 282 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4 [all …]
D	load-local-i32.ll	39 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} 49 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}} 50 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} 59 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4{{$}} 60 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:5 offset1:6{{$}} 61 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7{{$}} 62 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
D	local-64.ll	125 ; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:15 offset… 135 ; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1 144 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:31 of… 145 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:29 of… 155 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:3 off… 156 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1
D	ds_read2_offset_order.ll	`7 ; offset0 is larger than offset1 11 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3 12 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:14 offset1:12`
D	dagcombine-reassociate-bug.ll	`16 %offset0 = add i64 %offset, 1027 17 %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0`
D	ds_read2_superreg.ll	40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset… 115 ; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} 132 ; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} 133 ; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}} 134 ; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}} 175 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 …
D	scratch-buffer.ll	`60 %offset0 = load i32, i32 addrspace(1)* %offsets 61 %scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %offset0 62 store i32 %offset0, i32* %scratchptr0`
/external/brotli/c/enc/
D	backward_references.c	`29 size_t offset0 = distance_plus_3 - (size_t)dist_cache[0]; in ComputeDistanceCode() local 35 } else if (offset0 < 7) { in ComputeDistanceCode() 36 return (0x9750468 >> (4 * offset0)) & 0xF; in ComputeDistanceCode()`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
D	eh-return32.ll	`18 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp) 36 ; CHECK: lw $4, [[offset0]]($sp) 60 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp) 76 ; CHECK: lw $4, [[offset0]]($sp)`
D	eh-return64.ll	`19 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp) 37 ; CHECK: ld $4, [[offset0]]($sp) 63 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp) 79 ; CHECK: ld $4, [[offset0]]($sp)`
/external/llvm/test/CodeGen/Mips/
D	eh-return32.ll	`18 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp) 36 ; CHECK: lw $4, [[offset0]]($sp) 60 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp) 76 ; CHECK: lw $4, [[offset0]]($sp)`
D	eh-return64.ll	`19 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp) 37 ; CHECK: ld $4, [[offset0]]($sp) 63 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp) 79 ; CHECK: ld $4, [[offset0]]($sp)`
/external/tensorflow/tensorflow/tools/graph_transforms/
D	fold_old_batch_norms.cc	`243 std::vector<float> offset0(offset_values); in FuseBatchNormWithConvConcat() local 253 offset0.erase(offset0.begin() + split_cols, offset0.end()); in FuseBatchNormWithConvConcat() 262 FuseScaleOffsetToConvWeights(scale0, offset0, concat_node_match.inputs[0], in FuseBatchNormWithConvConcat()`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
D	DSInstructions.td	43 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1 72 bits<8> offset0; 76 let offset0 = !if(ds.has_offset, offset{7-0}, ?); 126 offset0:$offset0, offset1:$offset1, gds:$gds), 127 "$addr, $data0, $data1$offset0$offset1$gds"> { 193 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds), 194 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> { 240 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds), 241 "$vdst, $addr$offset0$offset1$gds"> { 720 (v2i32 (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))), [all …]

12 3 4

art
bionic
bootable
build
cts
dalvik
developers
development
device
external
frameworks
hardware
kernel
libcore
libnativehelper
packages
pdk
platform_testing
sdk
system
test
toolchain
tools