op4 (reference) in projects: external - OpenGrok search results

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Searched refs:op4 (Results 1 – 25 of 49) sorted by relevance

/external/llvm/test/Bitcode/
D	pr18704.ll	25 ; <STRUCT_NAME abbrevid=7 op0=115 op1=116 op2=114 op3=117 op4=99 op5=116 op6=46 op7=112 op8=97 o… 41 ; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> 42 ; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> 43 ; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> 44 ; <GLOBALVAR op0=4 op1=1 op2=25 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> 45 ; <GLOBALVAR op0=6 op1=1 op2=26 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> 46 ; <GLOBALVAR op0=8 op1=1 op2=27 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> 47 ; <GLOBALVAR abbrevid=4 op0=10 op1=1 op2=28 op3=3 op4=0 op5=0/> 48 ; <GLOBALVAR abbrevid=4 op0=6 op1=1 op2=26 op3=3 op4=0 op5=0/> 49 ; <GLOBALVAR abbrevid=4 op0=13 op1=1 op2=31 op3=3 op4=0 op5=0/> [all …]
D	module_hash.ll	3 ; MOD1: <HASH op0={{[0-9]}} op1={{[0-9]}} op2={{[0-9]}} op3={{[0-9]}} op4={{[0-9]}} (match)/> 5 ; MOD2: <HASH op0={{[0-9]}} op1={{[0-9]}} op2={{[0-9]}} op3={{[0-9]}} op4={{[0-9]}} (match)/> 24 …9]]] op1=[[HASH1_2:[0-9]]] op2=[[HASH1_3:[0-9]]] op3=[[HASH1_4:[0-9]]] op4=[[HASH1_5:[0-9]]] … 25 …9]]] op1=[[HASH2_2:[0-9]]] op2=[[HASH2_3:[0-9]]] op3=[[HASH2_4:[0-9]]] op4=[[HASH2_5:[0-9]]] … 28 …brevid={{[0-9]}} op0=[[HASH1_1]] op1=[[HASH1_2]] op2=[[HASH1_3]] op3=[[HASH1_4]] op4=[[HASH1_5]]/> 29 …brevid={{[0-9]}} op0=[[HASH2_1]] op1=[[HASH2_2]] op2=[[HASH2_3]] op3=[[HASH2_4]] op4=[[HASH2_5]]/>
D	thinlto-function-summary-refgraph.ll	14 ; CHECK-DAG: <PERMODULE {{.}} op0=[[MAINID:[0-9]+]] op1=0 {{.}} op3=1 op4=[[FUNCID:[0-9]+]] op… 16 ; CHECK-DAG: <PERMODULE {{.}} op0=[[WID:[0-9]+]] op1=5 {{.}} op3=1 op4=[[GLOBALVARID:[0-9]+]] … 19 ; CHECK-DAG: <PERMODULE {{.}} op0=[[XID:[0-9]+]] op1=1 {{.}} op3=1 op4=[[FOOID:[0-9]+]] op5=[[… 23 ; CHECK-DAG: <PERMODULE {{.}} op0=[[YID:[0-9]+]] op1=8 {{.}} op3=0 op4=[[FUNC2ID:[0-9]+]] op5=… 27 ; CHECK-DAG: <PERMODULE {{.}} op0=[[ZID:[0-9]+]] op1=3 {{.}} op3=0 op4=[[FUNC2ID:[0-9]+]] op5=…
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
D	pr18704.ll	25 ; <STRUCT_NAME abbrevid=7 op0=115 op1=116 op2=114 op3=117 op4=99 op5=116 op6=46 op7=112 op8=97 o… 41 ; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> 42 ; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> 43 ; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> 44 ; <GLOBALVAR op0=4 op1=1 op2=25 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> 45 ; <GLOBALVAR op0=6 op1=1 op2=26 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> 46 ; <GLOBALVAR op0=8 op1=1 op2=27 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> 47 ; <GLOBALVAR abbrevid=4 op0=10 op1=1 op2=28 op3=3 op4=0 op5=0/> 48 ; <GLOBALVAR abbrevid=4 op0=6 op1=1 op2=26 op3=3 op4=0 op5=0/> 49 ; <GLOBALVAR abbrevid=4 op0=13 op1=1 op2=31 op3=3 op4=0 op5=0/> [all …]
D	module_hash.ll	3 ; MOD1: <HASH op0={{[0-9]}} op1={{[0-9]}} op2={{[0-9]}} op3={{[0-9]}} op4={{[0-9]}} (match)/> 5 ; MOD2: <HASH op0={{[0-9]}} op1={{[0-9]}} op2={{[0-9]}} op3={{[0-9]}} op4={{[0-9]}} (match)/> 24 …9]]] op1=[[HASH1_2:[0-9]]] op2=[[HASH1_3:[0-9]]] op3=[[HASH1_4:[0-9]]] op4=[[HASH1_5:[0-9]]]/> 25 …9]]] op1=[[HASH2_2:[0-9]]] op2=[[HASH2_3:[0-9]]] op3=[[HASH2_4:[0-9]]] op4=[[HASH2_5:[0-9]]]/> 28 …brevid={{[0-9]}} op0=[[HASH1_1]] op1=[[HASH1_2]] op2=[[HASH1_3]] op3=[[HASH1_4]] op4=[[HASH1_5]]/> 29 …brevid={{[0-9]}} op0=[[HASH2_1]] op1=[[HASH2_2]] op2=[[HASH2_3]] op3=[[HASH2_4]] op4=[[HASH2_5]]/>
D	thinlto-function-summary-refgraph.ll	`43 ; op0=main op4=func op5=func 44 ; CHECK-DAG: <PERMODULE {{.}} op0=11 op1=0 {{.}} op4=1 op5=2 op6=2/> 46 ; op0=W op4=globalvar op5=func3 47 ; CHECK-DAG: <PERMODULE {{.}} op0=6 op1=5 {{.}} op4=1 op5=1 op6=5/> 50 ; op0=X op4=foo op5=foo 51 ; CHECK-DAG: <PERMODULE {{.}} op0=7 op1=1 {{.}} op4=1 op5=4 op6=4/> 55 ; op0=Y op4=func2 56 ; CHECK-DAG: <PERMODULE {{.}} op0=8 op1=72 {{.}} op4=0 op5=3/> 60 ; op0=Z op4=func2 61 ; CHECK-DAG: <PERMODULE {{.}} op0=9 op1=3 {{.}} op4=0 op5=3/>`
D	thinlto-alias2.ll	`7 ; CHECK-NEXT: <PERMODULE {{.*}} op4=0 op5=[[ALIASID:[0-9]+]]/>`
/external/llvm/test/Transforms/SLPVectorizer/X86/
D	propagate_ir_flags.ll	`26 %op4 = lshr exact i32 %load4, 1 31 store i32 %op4, i32* %idx4, align 4 52 %op4 = lshr exact i32 %load4, 1 57 store i32 %op4, i32* %idx4, align 4 78 %op4 = add nsw i32 %load4, 1 83 store i32 %op4, i32* %idx4, align 4 104 %op4 = add i32 %load4, 1 109 store i32 %op4, i32* %idx4, align 4 130 %op4 = add nuw i32 %load4, 1 135 store i32 %op4, i32* %idx4, align 4 [all …]`
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
D	ARMInstrNEON.td	1815 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 1817 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 1821 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 1823 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 1829 bits<2> op17_16, bits<5> op11_7, bit op4, 1832 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 1836 bits<2> op17_16, bits<5> op11_7, bit op4, 1839 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 1845 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 1848 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), [all …]
D	ARMInstrFormats.td	1429 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1451 let Inst{4} = op4; 1489 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1510 let Inst{4} = op4; 1515 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1518 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1549 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1552 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1692 bit op5, bit op4, 1703 let Inst{4} = op4; [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
D	propagate_ir_flags.ll	`26 %op4 = lshr exact i32 %load4, 1 31 store i32 %op4, i32* %idx4, align 4 52 %op4 = lshr exact i32 %load4, 1 57 store i32 %op4, i32* %idx4, align 4 78 %op4 = add nsw i32 %load4, 1 83 store i32 %op4, i32* %idx4, align 4 104 %op4 = add i32 %load4, 1 109 store i32 %op4, i32* %idx4, align 4 130 %op4 = add nuw i32 %load4, 1 135 store i32 %op4, i32* %idx4, align 4 [all …]`
/external/tensorflow/tensorflow/java/src/test/java/org/tensorflow/
D	OperationTest.java	`61 Operation op4 = g.operation("op1"); in operationEquality() local 66 assertEquals(op1, op4); in operationEquality() 67 assertEquals(op1.hashCode(), op4.hashCode()); in operationEquality() 68 assertEquals(op3, op4); in operationEquality() 70 assertNotEquals(op2, op4); in operationEquality() 84 Operation op4 = g.operation("op1"); in operationCollection() local 86 ops.addAll(Arrays.asList(op1, op2, op3, op4)); in operationCollection() 91 assertTrue(ops.contains(op4)); in operationCollection()`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
D	ARMInstrNEON.td	2525 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 2527 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2531 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 2533 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2539 bits<2> op17_16, bits<5> op11_7, bit op4, 2542 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2546 bits<2> op17_16, bits<5> op11_7, bit op4, 2549 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2589 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 2592 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), [all …]
D	ARMInstrFormats.td	1688 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1710 let Inst{4} = op4; 1808 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1829 let Inst{4} = op4; 1863 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1866 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1937 class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1959 let Inst{4} = op4; 2005 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 2008 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { [all …]
/external/llvm/lib/Target/ARM/
D	ARMInstrNEON.td	2434 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 2436 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2440 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 2442 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2448 bits<2> op17_16, bits<5> op11_7, bit op4, 2451 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2455 bits<2> op17_16, bits<5> op11_7, bit op4, 2458 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2498 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 2501 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), [all …]
D	ARMInstrFormats.td	1656 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1678 let Inst{4} = op4; 1776 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1797 let Inst{4} = op4; 1831 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1834 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1905 class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1927 let Inst{4} = op4; 1973 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1976 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { [all …]
/external/one-true-awk/
D	awkgram.y	391 { $$ = op4(SPLIT, $3, makearr($5), $7, (Node)STRING); } 393 { $$ = op4(SPLIT, $3, makearr($5), (Node)makedfa($7, 1), (Node )REGEXPR); } 395 { $$ = op4(SPLIT, $3, makearr($5), NIL, (Node)STRING); } /* default / 399 { $$ = op4($1, NIL, (Node)makedfa($3, 1), $5, rectonode()); } 402 $$ = op4($1, NIL, (Node)makedfa(strnode($3), 1), $5, rectonode()); 404 $$ = op4($1, (Node )1, $3, $5, rectonode()); } 406 { $$ = op4($1, NIL, (Node)makedfa($3, 1), $5, $7); } 409 $$ = op4($1, NIL, (Node)makedfa(strnode($3), 1), $5, $7); 411 $$ = op4($1, (Node *)1, $3, $5, $7); }
D	ytab.c	3290 { (yyval.p) = op4(SPLIT, (yyvsp[-5].p), makearr((yyvsp[-3].p)), (yyvsp[-1].p), (Node)STRING); } in yyparse() 3296 …{ (yyval.p) = op4(SPLIT, (yyvsp[-5].p), makearr((yyvsp[-3].p)), (Node)makedfa((yyvsp[-1].s), 1), … in yyparse() 3302 { (yyval.p) = op4(SPLIT, (yyvsp[-3].p), makearr((yyvsp[-1].p)), NIL, (Node)STRING); } in yyparse() 3320 …{ (yyval.p) = op4((yyvsp[-5].i), NIL, (Node)makedfa((yyvsp[-3].s), 1), (yyvsp[-1].p), rectonode()… in yyparse() 3327 …(yyval.p) = op4((yyvsp[-5].i), NIL, (Node)makedfa(strnode((yyvsp[-3].p)), 1), (yyvsp[-1].p), rect… in yyparse() 3329 (yyval.p) = op4((yyvsp[-5].i), (Node )1, (yyvsp[-3].p), (yyvsp[-1].p), rectonode()); } in yyparse() 3335 …{ (yyval.p) = op4((yyvsp[-7].i), NIL, (Node)makedfa((yyvsp[-5].s), 1), (yyvsp[-3].p), (yyvsp[-1].… in yyparse() 3342 …(yyval.p) = op4((yyvsp[-7].i), NIL, (Node)makedfa(strnode((yyvsp[-5].p)), 1), (yyvsp[-3].p), (yyv… in yyparse() 3344 (yyval.p) = op4((yyvsp[-7].i), (Node *)1, (yyvsp[-5].p), (yyvsp[-3].p), (yyvsp[-1].p)); } in yyparse()
/external/llvm/test/FileCheck/
D	simple-var-capture.txt	`9 op4 r30, r18, r21 11 ; CHECK-NEXT: op4 {{r[0-9]+}}, [[REGa]], [[REGb]]`
D	var-ref-same-line.txt	`12 op4 g1, g2, g1`
/external/swiftshader/third_party/llvm-7.0/llvm/test/FileCheck/
D	simple-var-capture.txt	`9 op4 r30, r18, r21 11 ; CHECK-NEXT: op4 {{r[0-9]+}}, [[REGa]], [[REGb]]`
D	var-ref-same-line.txt	`12 op4 g1, g2, g1`
/external/libvpx/libvpx/vpx_dsp/arm/
D	loopfilter_neon.c	314 uint8x8_t op4, uint8x8_t op3, uint8x8_t op2, uint8x8_t op1, in apply_15_tap_filter_8() argument 331 op4 = apply_15_tap_filter_8_kernel(flat2, p7, p5, p4, q2, p4, &sum); in apply_15_tap_filter_8() 352 uint8x16_t op4, uint8x16_t op3, uint8x16_t op2, uint8x16_t op1, in apply_15_tap_filter_16() argument 382 op4 = apply_15_tap_filter_16_kernel(flat2, p7, p5, p4, q2, p4, &sum0, &sum1); in apply_15_tap_filter_16() 488 uint8x##w##_t op4, uint8x##w##_t op3, uint8x##w##_t op2, \ 505 q2, q3, q4, q5, q6, q7, op6, op5, op4, op3, \ 954 uint8x##w##_t op4, uint8x##w##_t op3, uint8x##w##_t op2, \ 970 op5, op4, op3, op2, op1, op0, oq0, oq1, oq2, oq3, oq4, oq5, \ 981 op5, op4, op3, op2, op1, op0, oq0, oq1, oq2, oq3, oq4, oq5, oq6; in vpx_lpf_horizontal_16_neon() local 987 q2, q3, q4, q5, q6, q7, &op6, &op5, &op4, &op3, &op2, &op1, in vpx_lpf_horizontal_16_neon() [all …]
D	highbd_loopfilter_neon.c	198 uint16x8_t op4, uint16x8_t op3, uint16x8_t op2, uint16x8_t op1, in apply_15_tap_filter() argument 215 op4 = apply_15_tap_filter_kernel(flat2, p7, p5, p4, q2, p4, &sum); in apply_15_tap_filter() 321 const uint16x8_t q7, uint16x8_t op6, uint16x8_t op5, uint16x8_t op4, in filter16() argument 338 q4, q5, q6, q7, op6, op5, op4, op3, op2, op1, op0, in filter16() 670 q3, q4, q5, q6, q7, op6, op5, op4, op3, op2, op1, op0, oq0, oq1, oq2, oq3, in lpf_horizontal_16_kernel() local 681 p3, p2, p1, p0, q0, q1, q2, q3, q4, q5, q6, q7, &op6, &op5, &op4, in lpf_horizontal_16_kernel() 684 store_8x14(s, p, op6, op5, op4, op3, op2, op1, op0, oq0, oq1, oq2, oq3, oq4, in lpf_horizontal_16_kernel() 693 q3, q4, q5, q6, q7, op6, op5, op4, op3, op2, op1, op0, oq0, oq1, oq2, oq3, in lpf_vertical_16_kernel() local 710 p3, p2, p1, p0, q0, q1, q2, q3, q4, q5, q6, q7, &op6, &op5, &op4, in lpf_vertical_16_kernel() 715 store_7x8(s - 3, p, op6, op5, op4, op3, op2, op1, op0); in lpf_vertical_16_kernel()
/external/u-boot/post/lib_powerpc/
D	string.c	`26 ulong op4);`

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