/external/llvm/lib/Target/XCore/ |
D | XCoreInstrFormats.td | 36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 38 let Inst{15-11} = opc; 45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 46 : _F3R<opc, outs, ins, asmstr, pattern> { 50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 52 let Inst{31-27} = opc{8-4}; 54 let Inst{19-16} = opc{3-0}; 61 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr, 62 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> { 66 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
D | XCoreInstrFormats.td | 36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 38 let Inst{15-11} = opc; 45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 46 : _F3R<opc, outs, ins, asmstr, pattern> { 50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 52 let Inst{31-27} = opc{8-4}; 54 let Inst{19-16} = opc{3-0}; 61 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr, 62 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> { 66 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrEnc.td | 1 class Enc_COPROC_VX_3op_v<bits<15> opc> : OpcodeHexagon { 6 let Inst{31-16} = { opc{14-4}, src2}; 7 let Inst{13-0} = { opc{3}, src1, opc{2-0}, dst}; 196 class Enc_COPROC_VX_cmp<bits<13> opc> : OpcodeHexagon { 201 let Inst{31-16} = { 0b00011, opc{12-7}, src2{4-0} }; 202 let Inst{13-0} = { opc{6}, src1{4-0}, opc{5-0}, dst{1-0} }; 244 class Enc_COPROC_VX_p2op<bits<5> opc> : OpcodeHexagon { 249 let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} }; 250 let Inst{13-0} = { 1, src2{4-0}, opc{2-0}, dst{4-0} }; 266 class Enc_COPROC_VX_2op<bits<6> opc> : OpcodeHexagon { [all …]
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/external/wpa_supplicant_8/src/crypto/ |
D | milenage.c | 36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument 44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1() 57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1() 67 tmp1[i] ^= opc[i]; in milenage_f1() 88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument 96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345() 108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345() 114 tmp3[i] ^= opc[i]; in milenage_f2345() 124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345() 129 ck[i] ^= opc[i]; in milenage_f2345() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | SVEInstrFormats.td | 242 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty> 252 let Inst{18-17} = opc{2-1}; 253 let Inst{16} = opc{0}; 259 let Defs = !if(!eq (opc{0}, 1), [NZCV], []); 262 multiclass sve_int_ptrue<bits<3> opc, string asm> { 263 def _B : sve_int_ptrue<0b00, opc, asm, PPR8>; 264 def _H : sve_int_ptrue<0b01, opc, asm, PPR16>; 265 def _S : sve_int_ptrue<0b10, opc, asm, PPR32>; 266 def _D : sve_int_ptrue<0b11, opc, asm, PPR64>; 288 class sve_int_pfalse<bits<6> opc, string asm> [all …]
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D | AArch64InstrFormats.td | 1090 class CRmSystemI<Operand crmtype, bits<3> opc, string asm, 1097 let Inst{7-5} = opc; 1267 // case opc of 1274 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm, 1278 let Inst{24-21} = opc; 1284 class BranchReg<bits<4> opc, string asm, list<dag> pattern> 1285 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> { 1291 class SpecialReturn<bits<4> opc, string asm> 1292 : BaseBranchReg<opc, (outs), (ins), asm, "", []> { 1327 class AuthOneOperand<bits<3> opc, bits<1> M, string asm> [all …]
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/external/swiftshader/third_party/LLVM/test/TableGen/ |
D | DefmInsideMultiClass.td | 4 class Instruction<bits<4> opc, string Name> { 5 bits<4> opcode = opc; 9 multiclass basic_r<bits<4> opc> { 10 def rr : Instruction<opc, "rr">; 11 def rm : Instruction<opc, "rm">; 14 multiclass basic_s<bits<4> opc> { 15 defm SS : basic_r<opc>; 16 defm SD : basic_r<opc>; 19 multiclass basic_p<bits<4> opc> { 20 defm PS : basic_r<opc>; [all …]
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D | LetInsideMultiClasses.td | 4 class Instruction<bits<4> opc, string Name> { 5 bits<4> opcode = opc; 10 multiclass basic_r<bits<4> opc> { 12 def rr : Instruction<opc, "rr">; 13 def rm : Instruction<opc, "rm">; 17 def rx : Instruction<opc, "rx">; 20 multiclass basic_ss<bits<4> opc> { 22 defm SS : basic_r<opc>; 25 defm SD : basic_r<opc>;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
D | DefmInsideMultiClass.td | 7 class Instruction<bits<4> opc, string Name> { 8 bits<4> opcode = opc; 12 multiclass basic_r<bits<4> opc> { 13 def rr : Instruction<opc, "rr">; 14 def rm : Instruction<opc, "rm">; 17 multiclass basic_s<bits<4> opc> { 18 defm SS : basic_r<opc>; 19 defm SD : basic_r<opc>; 22 multiclass basic_p<bits<4> opc> { 23 defm PS : basic_r<opc>; [all …]
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D | LetInsideMultiClasses.td | 9 class Instruction<bits<4> opc, string Name> { 10 bits<4> opcode = opc; 15 multiclass basic_r<bits<4> opc> { 17 def rr : Instruction<opc, "rr">; 18 def rm : Instruction<opc, "rm">; 22 def rx : Instruction<opc, "rx">; 25 multiclass basic_ss<bits<4> opc> { 27 defm SS : basic_r<opc>; 30 defm SD : basic_r<opc>;
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/external/llvm/test/TableGen/ |
D | DefmInsideMultiClass.td | 7 class Instruction<bits<4> opc, string Name> { 8 bits<4> opcode = opc; 12 multiclass basic_r<bits<4> opc> { 13 def rr : Instruction<opc, "rr">; 14 def rm : Instruction<opc, "rm">; 17 multiclass basic_s<bits<4> opc> { 18 defm SS : basic_r<opc>; 19 defm SD : basic_r<opc>; 22 multiclass basic_p<bits<4> opc> { 23 defm PS : basic_r<opc>; [all …]
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D | LetInsideMultiClasses.td | 9 class Instruction<bits<4> opc, string Name> { 10 bits<4> opcode = opc; 15 multiclass basic_r<bits<4> opc> { 17 def rr : Instruction<opc, "rr">; 18 def rm : Instruction<opc, "rm">; 22 def rx : Instruction<opc, "rx">; 25 multiclass basic_ss<bits<4> opc> { 27 defm SS : basic_r<opc>; 30 defm SD : basic_r<opc>;
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPUInstrInfo.cpp | 33 unsigned opc = I->getOpcode(); in isUncondBranch() local 35 return (opc == SPU::BR in isUncondBranch() 36 || opc == SPU::BRA in isUncondBranch() 37 || opc == SPU::BI); in isUncondBranch() 42 unsigned opc = I->getOpcode(); in isCondBranch() local 44 return (opc == SPU::BRNZr32 in isCondBranch() 45 || opc == SPU::BRNZv4i32 in isCondBranch() 46 || opc == SPU::BRZr32 in isCondBranch() 47 || opc == SPU::BRZv4i32 in isCondBranch() 48 || opc == SPU::BRHNZr16 in isCondBranch() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86InstrAVX512.td | 798 multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr, 802 def r_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst), 808 def rk_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst), 817 def rkz_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst), 828 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr, 831 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst), 835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst), 842 defm m_Int : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst), 851 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr, 853 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>, [all …]
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D | X86InstrXOP.td | 14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> { 15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), 42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int, 44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src), 52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int, 54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), 62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int, [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrFormats.td | 430 string opc, string asm, string cstr, 437 let AsmString = !strconcat(opc, "${p}", asm); 445 string opc, string asm, string cstr, 450 let AsmString = !strconcat(opc, asm); 461 string opc, string asm, string cstr, 471 let AsmString = !strconcat(opc, "${s}${p}", asm); 489 string opc, string asm, list<dag> pattern> 491 opc, asm, "", pattern>; 493 string opc, string asm, list<dag> pattern> 495 opc, asm, "", pattern>; [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrFormats.td | 348 string opc, string asm, string cstr, 355 let AsmString = !strconcat(opc, "${p}", asm); 363 string opc, string asm, string cstr, 368 let AsmString = !strconcat(opc, asm); 379 string opc, string asm, string cstr, 389 let AsmString = !strconcat(opc, "${s}${p}", asm); 407 string opc, string asm, list<dag> pattern> 409 opc, asm, "", pattern>; 411 string opc, string asm, list<dag> pattern> 413 opc, asm, "", pattern>; [all …]
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/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
D | instr-a3xx.h | 35 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) argument 216 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) argument 217 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) argument 316 uint32_t opc : 4; member 422 uint32_t opc : 6; member 482 uint32_t opc : 4; member 490 switch (_OPC(3, cat3->opc)) { in instr_cat3_full() 539 uint32_t opc : 6; member 588 uint32_t opc : 5; member 719 uint32_t opc : 5; member [all …]
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D | ir3_cp.c | 68 if (src_instr->opc == OPC_META_FO) in is_eligible_mov() 75 if (src_instr->opc == OPC_META_PHI) in is_eligible_mov() 114 switch (opc_cat(instr->opc)) { in valid_flags() 121 valid_flags = ir3_cat2_absneg(instr->opc) | in valid_flags() 124 if (ir3_cat2_int(instr->opc)) in valid_flags() 149 valid_flags = ir3_cat3_absneg(instr->opc) | in valid_flags() 197 if ((instr->opc == OPC_LDL) && (n != 1)) in valid_flags() 200 if ((instr->opc == OPC_STL) && (n != 2)) in valid_flags() 206 if (is_atomic(instr->opc) && (n != 0)) in valid_flags() 209 if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G)) in valid_flags() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrFormats.td | 450 string opc, string asm, string cstr, 457 let AsmString = !strconcat(opc, "${p}", asm); 465 string opc, string asm, string cstr, 470 let AsmString = !strconcat(opc, asm); 481 string opc, string asm, string cstr, 491 let AsmString = !strconcat(opc, "${s}${p}", asm); 509 string opc, string asm, list<dag> pattern> 511 opc, asm, "", pattern>; 513 string opc, string asm, list<dag> pattern> 515 opc, asm, "", pattern>; [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrFormats.td | 879 class CRmSystemI<Operand crmtype, bits<3> opc, string asm, 886 let Inst{7-5} = opc; 1045 // case opc of 1052 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm, 1056 let Inst{24-21} = opc; 1062 class BranchReg<bits<4> opc, string asm, list<dag> pattern> 1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> { 1069 class SpecialReturn<bits<4> opc, string asm> 1070 : BaseBranchReg<opc, (outs), (ins), asm, "", []> { 1270 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm, [all …]
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
D | disasm-a2xx.c | 129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc } argument 439 #define INSTR(opc, name, fxn) [opc] = { name, fxn } argument 464 printf("%s", fetch_instructions[fetch->opc].name); in disasm_fetch() 465 fetch_instructions[fetch->opc].fxn(fetch); in disasm_fetch() 477 return (cf->opc == EXEC) || in cf_exec() 478 (cf->opc == EXEC_END) || in cf_exec() 479 (cf->opc == COND_EXEC) || in cf_exec() 480 (cf->opc == COND_EXEC_END) || in cf_exec() 481 (cf->opc == COND_PRED_EXEC) || in cf_exec() 482 (cf->opc == COND_PRED_EXEC_END) || in cf_exec() [all …]
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/external/mesa3d/src/gallium/drivers/etnaviv/ |
D | etnaviv_disasm.c | 38 uint32_t opc : 6; member 459 #define OPC(opc) [INST_OPCODE_##opc] = {#opc, print_opc_default} argument 460 #define OPC_MOV(opc) [INST_OPCODE_##opc] = {#opc, print_opc_mov} argument 461 #define OPC_TEX(opc) [INST_OPCODE_##opc] = {#opc, print_opc_tex} argument 462 #define OPC_IMM(opc) [INST_OPCODE_##opc] = {#opc, print_opc_imm} argument 523 const unsigned opc = instr->opc | (instr->opcode_bit6 << 6); in print_instr() local 524 const char *name = opcs[opc].name; in print_instr() 596 opcs[opc].print(&operands); in print_instr() 598 printf("unknown (%d)", instr->opc); in print_instr()
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/external/u-boot/drivers/mmc/ |
D | sh_mmcif.c | 337 u32 opc = cmd->cmdidx; in sh_mmcif_set_cmd() local 358 if (opc == MMC_CMD_SWITCH) in sh_mmcif_set_cmd() 380 if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || in sh_mmcif_set_cmd() 381 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) in sh_mmcif_set_cmd() 384 if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || in sh_mmcif_set_cmd() 385 opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { in sh_mmcif_set_cmd() 390 if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd() 391 opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) in sh_mmcif_set_cmd() 394 if (opc == MMC_CMD_SEND_OP_COND) in sh_mmcif_set_cmd() 397 if (opc == MMC_CMD_ALL_SEND_CID || in sh_mmcif_set_cmd() [all …]
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/external/libunwind/src/ia64/ |
D | Gscript.c | 267 enum ia64_script_insn_opcode opc; in compile_reg() local 275 opc = IA64_INSN_MOVE; in compile_reg() 286 opc = IA64_INSN_MOVE_STACKED_NAT; in compile_reg() 288 opc = IA64_INSN_MOVE_STACKED; in compile_reg() 296 opc = IA64_INSN_MOVE_NAT; in compile_reg() 302 opc = IA64_INSN_MOVE_SCRATCH_NAT; in compile_reg() 304 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg() 323 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg() 333 opc = IA64_INSN_MOVE_NO_NAT; in compile_reg() 337 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg() [all …]
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